AT89LP4052-20PI datasheet(56/90 Pages) ATMEL

56 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

22.2

Status Register

The current state of the memory may be accessed by reading the status register. The status reg-

ister is shown in Table 22-2.

22.3

DATA Polling

The AT89LP2052/LP4052 implements DATA polling to indicate the end of a programming cycle.

While the device is busy, any attempted read of the last byte written will return the data byte with

the MSB complemented. Once the programming cycle has completed, the true value will be

accessible. During Erase the data is assumed to be FFH and DATA polling will return 7FH.

When writing multiple bytes in a page, the DATA value will be the last data byte loaded before

programming begins, not the written byte with the highest physical address within the page.

22.4

Parallel Programming

Parallel Programming Mode is enabled by applying V

PP to the RST pin. The connections

required during parallel mode are shown in Figure 22-2. During parallel programming, Port 1 is

configured as an 8-bit wide bidirectional command bus. Data on P1 is strobed by a positive

pulse on the XTAL1 pin. No other clock is required. The interface is enabled by pulling CS (P3.2)

low. P3.1 acts as RDY/BSY, and will be pulled low to indicate that the device is busy regardless

of the state of CS.

Table 22-2.

Status

–––

–

LOAD

SUCCESS

WRTINH

BUSY

Bit

543

Symbol

Function

LOAD

Load flag. Cleared low by the load page buffer command and set high by the next memory write. This flag signals that

the page buffer was previously loaded with data by the load page buffer command.

SUCCESS

Success flag. Cleared low at the start of a programming cycle and will only be set high if the programming cycle

completes without interruption from the brownout detector.

WRTINH

Write Inhibit flag. Cleared low by the brownout detector (BOD) whenever programming is inhibited due to V

CC falling

below the minimum required programming voltage. If a BOD episode occurs during programming, the SUCCESS flag

will remain low after the cycle is complete. WRTINH low also forces BUSY low.

BUSY

Busy flag. Cleared low whenever the memory is busy programming or if write is currently inhibited.

AT89LP4052-20PI Datasheet(PDF) 56 Page - ATMEL Corporation

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