AT89LP4052-20PI datasheet(4/90 Pages) ATMEL

4 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

Block Diagram

Memory Organization

The AT89LP2052/LP4052 uses a Harvard Architecture with separate address spaces for pro-

gram and data memory. The program memory has a regular linear address space with support

for up to 64K bytes of directly addressable application code. The data memory has 256 bytes of

internal RAM which is divided into regions that may be accessed by different instruction classes.

The AT89LP2052/LP4052 does not support external RAM.

5.1

Program Memory

The AT89LP2052/LP4052 contains 2/4K bytes of on-chip In-System Programmable Flash mem-

ory for program storage. The Flash memory has an endurance of at least 10,000 write/erase

cycles. Section 22. “Programming the Flash Memory” on page 54 contains a detailed description

on Flash Programming in ISP or Parallel Programming mode. The reset and interrupt vectors

are located within the first 59 bytes of program memory (see Section 13. “Interrupts” on page

13). Constant tables can be allocated within the entire 2/4-Kbyte program memory address

space for access by the MOVC instruction.

Single Cycle

8051 CPU

2/4-Kbyte

Flash

256-Byte

RAM

Port 3

Configurable I/O

Port 1

Configurable I/O

UART

SPI

Timer 0

Timer 1

Analog

Comparator

Watchdog

Timer

Configurable

Oscillator

CPU Clock

Crystal or

Resonator

AT89LP4052-20PI Datasheet(PDF) 4 Page - ATMEL Corporation