ATAM894 datasheet(85/97 Pages) ATMEL

85 / 97 page

4679D–4BMCU–05/05

ATAM894

7.1.1.1

Control Byte Format

7.1.2

EEPROM

The EEPROM has a size of 2

× 512 bits and is organized as 32 x 16-bit matrix each. To read

and write data to and from the EEPROM the serial interface must be used. The interface sup-

ports one and two byte write accesses and one to n-byte read accesses to the EEPROM.

7.1.2.1

EEPROM - Operating Modes

The operating modes of the EEPROM are defined via the control byte. The control byte contains

the row address, the mode control bits and the read/not-write bit that is used to control the direc-

tion of the following transfer. A '0' defines a write access and a '1' a read access. The five

address bits select one of the 32 rows of the EEPROM memory to be accessed. For all

accesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer must

be read or overwritten via the serial interface. The two mode control bits C

1 and C2 define in

which order the accesses to the buffer are performed: High byte – low byte or low byte – high

byte. The EEPROM also supports auto increment and auto decrement read operations. After

sending the start address with the corresponding mode, consecutive memory cells can be read

row by row without transmission of the row addresses.

Two special control bytes enable the complete initialization of EEPROM with '0' or with '1'.

7.1.2.2

Write Operations

The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the START

condition followed by a write control byte and one or two data bytes from the master. It is com-

pleted via the STOP condition from the master after the acknowledge cycle.

The programming cycle consists of an erase cycle (write “zeros”) and the write cycle (write

“ones”). Both cycles together take about 10 ms.

7.1.2.3

Acknowledge Polling

If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will

not acknowledge until the write cycle is finished. This can be used to detect the end of the write

cycle. The master must acknowledge polling by sending a start condition followed by the control

byte. If the device is still busy with the write cycle, it will not return an acknowledge and the mas-

ter has to generate a stop condition or perform further acknowledge polling sequences. If the

cycle is complete, it returns an acknowledge and the master can proceed with the next read or

write cycle.

EEPROM Address

Mode Control Bits

Read/

NWrite

Start

A4A3A2

A1A0

R/NW

Ackn

Start

Control byte

Ackn

Data byte

Ackn

Data byte

Ackn

Stop

ATAM894 Datasheet(PDF) 85 Page - ATMEL Corporation

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