ATAM894 datasheet(61/97 Pages) ATMEL

61 / 97 page

4679D–4BMCU–05/05

ATAM894

Figure 6-38.

Block Diagram of the Synchronous Serial Interface

6.3.4.3

General SSI Operation

The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buffers the

receive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for inter-

mediate storage of data to be serially output. Both buffers are directly accessible by software.

Transferring the parallel buffer data into and out of the shift register is controlled automatically by

the SSI control, so that both single byte transfers or continuous bit streams can be supported.

The SSI can generate the shift clock (SC) either from one of several on-chip clock sources or

accept an external clock. The external shift clock is output on, or applied to the Port BP40.

Selection of an external clock source is performed by the Serial Clock Direction control bit

(SCD). In the combinational modes, the required clock is selected by the corresponding timer

mode.

The SSI can operate in three data transfer modes - synchronous 8-bit shift mode, MCL compati-

ble 9-bit shift modes or 8-bit pseudo MCL protocol (without acknowledge-bit).

External SSI clocking is not supported in these modes. The SSI should thus generate and has

full control over the shift clock so that it can always be regarded as an MCL Bus Master device.

All directional control of the external data port used by the SSI is handled automatically and is

dependent on the transmission direction set by the Serial Data Direction (SDD) control bit. This

control bit defines whether the SSI is currently operating in Transmit (TX) mode or Receive (RX)

mode.

Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. In

the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the telegram for

handshaking purposes (see section ”MCL Bus Protocol” on page 65).

At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register

and proceeds immediately to shift data serially out. At the same time, incoming data is shifted

into the shift register input. This incoming data is automatically loaded into the receive buffer

when the complete telegram has been received. Thus, data can be simultaneously received and

transmitted if required.

8-bit Shift Register

MSB

LSB

Shift_CL

SIC1

SIC2

SISC

Control

STB

SRB

Timer 2/Timer 3

Output

INT3

I/O-bus

SSI-Control

TOG2

POUT

T1OUT

SYSCL

MCL_SC

MCL_SD

Transmit

Buffer

Receive

Buffer

SCI

ATAM894 Datasheet(PDF) 61 Page - ATMEL Corporation

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