VC0736 datasheet(24/127 Pages) NEXTCHIP

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NVP6124

Data sheet

02.11.2015 (REV 0.2)

22/125

4-CH AHD2.0 RX and 9-CH Audio Codec

￭ Example of 148.5MHz(960H) D1 Data Output Mode with Channel ID

1. In case of VDO1 output port and VCLK1 output clock use.

2. Set VDO1 output(CH_OUT_SEL1,BANK1,0xC8[3:0] = 0x8) and VCLK1 output (VCLK1_SEL,

BANK1,0xCC[6:4] = 0x6 or 0x7) .

3. Set Channel ID Type (Refer to CHID_TYPE(Bank0, 0x54[2:0]) Register Description)

4. And then NVP6124 generate 148.5MHz(960H) clock and data output (Figure 2.15)

If you want to confirm the 148.5MHz Data using FPGA or Other device, Execute 5~11 item in next page.

NVP6124

VDO1

VCLK01

27MHz clock

input

CH1

CH2

CH3

CH4

CH1

CH2

CH3

CH4

CH1

CH2

CH3

CH4

CH1

CH2

CH3

CH4

CH1

CH2

CH1

CH2

CH1

CH3

CH1

CH3

CH1

CH4

CH1

CH4

CH1

148.5MHz data output

148.5MHz clock

148.5MHz data output

37.125MHz data

VIN1

VIN2

VIN3

VIN4

CH1

CH2

CH3

CH4

Figure 2.15. NVP6124 generate 148.5MHz(960H) clock and data output

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