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VC0736 Datasheet(PDF) 30 Page - NEXTCHIP Co,Ltd

Part # VC0736
Description  4-CH AHD2.0 RX and 9-CH Audio Codec
PDF  127 Pages
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Manufacturer  NEXTCHIP [NEXTCHIP Co,Ltd]
Direct Link  https://www.nextchip.com/en/
Logo NEXTCHIP - NEXTCHIP Co,Ltd

VC0736 Datasheet(HTML) 30 Page - NEXTCHIP Co,Ltd

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NVP6124
Data sheet
02.11.2015 (REV 0.2)
28/125
4-CH AHD2.0 RX and 9-CH Audio Codec
Table 3.1. Sampling & PCM coding setting
BANK1
8K/8bit
8K/16bit
16K/8bit
16K/16bit
32K/8bit
32K/16bit
ADDR
VALUE
ADDR
VALUE
ADDR
VALUE
ADDR
VALUE
ADDR
VALUE
ADDR
VALUE
Linear
PCM
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0
0
1
00
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0
0
0
00
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0
1
1
00
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0
1
0
00
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
1
1
1
00
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
1
1
0
00
Unsigned
Linear
PCM
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0
0
1
01
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0
0
0
01
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0
1
1
01
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0
1
0
01
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
1
1
1
01
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
1
1
0
01
G.711
U-law
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
0
0
1
10
0
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
0
0
0
10
0
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
0
1
1
10
0
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
0
1
0
10
0
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
1
1
1
10
0
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
1
1
0
10
0
G.711
A-law
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
0
0
1
10
1
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
0
0
0
10
1
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
0
1
1
10
1
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
0
1
0
10
1
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
1
1
1
10
1
0x00[0]
0x07[3]
0x07[2]
0x08[5:4]
0x08[6]
1
1
0
10
1
DSP / SSP / I2S interfaces are supported as output data format. In addition, slave mode and
master mode are also supported. At slave mode, input clock and synchronized signal come from
external ICs, however Master mode generates clock and synchronized signal in itself.
3.2.1 Data Output Interface
NVP6124 outputs "Record Output" using ACLK_REC, ASYNC_REC, ADATA_REC and
DATA_SP.
ACLK_REC is a reference clock signal for Record Output Data and ASYNC_REC
is a reference synchronization signal for Record Output Data. ADATA_REC and ADATA_SP
are synchronized Record Output, data with reference clock and reference synchronized signal.
Table 3.2 Record Output Interface configuration
BANK1
DSP
SSP
I2S
ADDR
VALUE
ADDR
VALUE
ADDR
VALUE
Master
0x07[0]
0x07[1]
0x07[7]
1
0
1
0x07[0]
0x07[1]
0x07[7]
1
1
1
0x07[0]
0x07[1]
0x07[7]
0
0
1
Slave
0x07[0]
0x07[1]
0x07[7]
1
0
0
0x07[0]
0x07[1]
0x07[7]
1
1
0
0x07[0]
0x07[1]
0x07[7]
0
0
0
ACLK_REC is a reference clock of Record Output Data and ASYNC_REC is reference
synchronized signal. ACLK_REC and ASYNC_REC signal support slave mode accepted
external signals and master mode generating clock and synchronization signal in itself. And



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