 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
VC0736 Datasheet(PDF) 31 Page - NEXTCHIP Co,Ltd |
|
|
|||||||||||||||||||||||||||||
VC0736 Datasheet(HTML) 31 Page - NEXTCHIP Co,Ltd |
|
|
31 / 127 page  NVP6124 Data sheet 02.11.2015 (REV 0.2) 29/125 4-CH AHD2.0 RX and 9-CH Audio Codec DSP/SSP/I2S interfaces are supported by configuration of these pins defined by internal register setting value. Figure 3.1, 3.2, 3.3 shows timing diagram of I2S, DSP, and SSP mode, respectively. These figures show timing relation among ASYNC_REC, ACLK_REC and ADTA_REC, and ADATA_SP is outputted using same interface method of ADATA_REC. Polarity of ACLK_REC clock is changed by setting of internal register value (RM_CLK, 0x07[6], BANK1). MSB MSB 1/fs data0 data1 ASYNC_REC ACLK_REC ADATA_REC Figure 3.1 I2S mode MSB MSB 1/fs data0 data1 ASYNC_REC ACLK_REC ADATA_REC Figure 3.2 DSP mode MSB MSB 1/fs data0 data1 ASYNC_REC ACLK_REC ADATA_REC Figure 3.3 SSP mode |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
