LAN91C100FD datasheet(28/67 Pages) SMSC

28 / 67 page

SMSC DS – LAN91C100FD REV. B

Page 28

Rev. 01-20-06

BANK2

OFFSET

NAME

TYPE

SYMBOL

MMU COMMAND REGISTER

WRITE ONLY

BUSY Bit Readable

MMUCR

This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control.

The three command bits determine the command issued as described below:

HIGH

BYTE

LOW

BYTE

COMMAND

N0/BUSY

COMMAND SET:

xyz

000

NOOP - NO OPERATION

001

ALLOCATE MEMORY FOR TX - N2,N1,N0 defines the amount of memory requested as (value + 1) * 256

bytes. Namely N2,N1,N0 = 1 will request 2 * 256 = 512 bytes. A shift-based divide by 256 of the packet

length yields the appropriate value to be used as N2,N1,N0. Immediately generates a completion code at the

ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful completion.

N2,N1,N0 are ignored by the LAN91C100FD but should be implemented in LAN91C100FD software drivers

for LAN9000 compatibility.

010

RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts, resets packet

FIFO pointers.

011

REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has completed processing of present

receive frame. This command removes the receive packet number from the RX FIFO and brings the next

receive frame (if any) to the RX area (output of RX FIFO).

100

REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all memory used by the packet

presently at the RX FIFO output. The MMU busy time after issuing REMOVE and RELEASE command

depends on the time when the busy bit is cleared. The time from issuing REMOVE and RELEASE

command on the last receive packet to the time when receive FIFO is empty depends on RX INT bit turning

low. An alternate approach can be checking the read RX FIFO register.

101

RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the PACKET NUMBER

frames, after reading their completion status. Can be used following 3) to release receive packet memory in

a more flexible way than 4).

110

ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just

loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER.

111

RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO holding the packet numbers

awaiting transmission and the TX Completion FIFO.

This

command

provides

mechanism

for

canceling packet transmissions, and reordering or bypassing the transmit queue. The RESET TX FIFOs

command should only be used when the transmitter is disabled. Unlike the RESET MMU command, the

RESET TX FIFOs does not release any memory.

Note 1: Bits N2,N1,N0 bits are ignored by the LAN91C100FD but should be used for command 0 to preserve software

compatibility with the LAN91C92 and future devices. They should be zero for all other commands.

LAN91C100FD Datasheet(PDF) 28 Page - SMSC Corporation

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