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BOARD DESIGN AND LAYOUT CONSIDERATIONS

AGND, DGND Pins

MOUTL, MOUTR Pins

BCK and LRCK Pins (in Master Mode), DOUT Pin

System Clock

PCM1850A

PCM1851A

SLES173 – MARCH 2006

APPLICATION INFORMATION (continued)

The digital and analog power supply lines to the PCM1850A/1851A must be bypassed to the corresponding

ground pins with 0.1-

µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize

the dynamic performance of the ADC.

To maximize the dynamic performance of the PCM1850A/1851A, the analog and digital grounds are not

connected internally. These grounds must have low impedance to avoid digital noise feeding back into the

analog ground. Therefore, they should be connected directly to each other under the parts to reduce the potential

of a noise problem.

A 0.33-

µF capacitor is recommended as the ac-coupling capacitor, which gives a 2.4- to 8.5-Hz cutoff frequency.

pin, but a signal source resistance less than 1 k

Ω is recommended for these pins in order to keep accuracy of

the gain control command and to maintain crosstalk performance.

An ac-coupled light load is recommended; a 2.2-

µF capacitor with a 10-kΩ load gives a 7.2-Hz cutoff frequency.

capacitors are recommended to ensure low source impedance of the ADC references. These capacitors should

These pins have enough load-driving capability. However, if the output line is long, locating a buffer near the

PCM1850A/1851A and minimizing load capacitance is recommended in order to minimize the digital-analog

crosstalk and maximize the dynamic performance of the ADC.

Because the PCM1850A/1851A operates based on a system clock, the quality of the system clock can influence

dynamic performance. Therefore, it is recommended to consider the system clock duty, jitter, and the time

difference between the system clock transition and the BCK or LRCK transition in slave mode.

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