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PCM1850APJTG4 Datasheet(PDF) 15 Page - Burr-Brown (TI) |
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PCM1850APJTG4 Datasheet(HTML) 15 Page - Burr-Brown (TI) |
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15 / 32 page ![]() www.ti.com POWER-ON-RESET SEQUENCE System Clock 2.6 V 2.2 V 1.8 V Internal Reset DOUT Zero Data Normal Data Reset VDD Release From Reset 1024 System Clocks 4500/fS T0014-10 PCM1850A PCM1851A SLES173 – MARCH 2006 The PCM1850A/1851A has an internal power-on-reset circuit, and initialization (reset) is performed automatically at the time that the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical) and for 1024 system clocks after VDD > 2.2 V (typical), the PCM1850A/1851A stays in the reset state and the digital output is forced to zero. The digital output is valid after the reset state is released and the time of 4500/fS has passed. At the moment of the power-on-reset release, the PCM1850A/1851A does not need a system clock. Figure 21 illustrates the internal power-on-reset timing and the digital output for power-on reset. Figure 21. Internal Power-On-Reset Timing 15 Submit Documentation Feedback |
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