ADMV8502ACCZ-R7 datasheet(3/32 Pages) AD

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Data Sheet

ADMV8502

SPECIFICATIONS

analog.com

Rev. 0 | 3 of 32

TA = 25°C, unless otherwise noted.

Table 1. Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

FREQUENCY RANGE (fCENTER)

225

MHz

BANDWIDTH (3 dB)

BANDWIDTH ADJUSTABILITY

±2

RESOLUTION

8 bits per filter

REJECTION (20 dB)

Low-Side

0.85 × fCENTER

GHz

High-Side

1.17 × fCENTER

GHz

RE-ENTRY FREQUENCY

GHz

≤30 dB

INSERTION LOSS

3.5

RETURN LOSS

DYNAMIC PERFORMANCE

Input Compression (P0.1dB)

dBm

Input Third-Order Intercept (IP3)

Input power (PIN) = 5 dBm, f1 is Input Frequency 1, and f2

is Input Frequency 2

Low-Side IP3

dBm

f1 = 0.9 × fCENTER , f2 = 0.95 × fCENTER

High-Side IP3

dBm

f1 = 1.05 × fCENTER , f2 = 1.1 × fCENTER

In-Band IP3

dBm

f1 = fCENTER − 5 kHz, f2 = fCENTER + 5 kHz

Group Delay

At fCENTER = 90 MHz

Amplitude Settling Time

<15

μs

To within ≤1 dB of static insertion loss

Phase Settling Time

<20

µs

To within ≤2° of static phase

Drift Rate

Amplitude

–0.01

dB/°C

At fCENTER = 146 MHz

Frequency

–50

ppm/°C

SUPPLY VOLTAGE

VSS

–2.6

–2.5

–2.4

VDD

+3.2

+3.3

+3.4

SUPPLY CURRENT (STATIC)

Static

VSS Current (ISS)

µA

VDD Current (IDD)

125

µA

Dynamic

IDD

fSCLK/4

Where fSCLK is the SCLK toggle frequency in MHz,

for example, continuous serial peripheral interface (SPI)

writing at 10 MHz yields 2.5 mA of dynamic supply

current

LOGIC (RST, CS, SCLK, SDI, SDO, and SFL)

Logic Low

−0.3

+0.8

Logic High

+1.2

+3.3

+3.6

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