ADMV8502ACCZ-R7 datasheet(4/32 Pages) AD

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Data Sheet

ADMV8502

SPECIFICATIONS

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TIMING SPECIFICATIONS

Table 2. Timing Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

RST low time to perform reset

SCLK cycle time (write)

SCLK cycle time (read)

2.5

SCLK high time

2.5

SCLK low time

CS falling edge to SCLK rising edge setup time

SCLK rising edge to hold time

Minimum CS high time for latching in data (for multiple SPI transactions)

CS rising edge to next SCLK rising edge ignore

SDI data setup time

t10

SDI data hold time

t11

SFL falling edge (exiting SFL mode) to CS falling edge time (start of SPI transaction)

t12

CS rising edge (end of SPI transaction) to SFL rising edge time (entering SFL mode)

t13

SFL rising edge to CS falling edge time

t14

CS cycle time (SFL mode)

t15

2.5

CS high time (SFL mode)

t16

2.5

CS low time (SFL mode)

t17

SCLK falling edge to SDO valid (load capacitance (CL) = 10 pF)

t18

SDO rise and fall time (CL = 10 pF)

t19

CS rising edge to SDO tristate (CL = 10 pF)

Timing Diagram

Figure 2. Timing Diagram

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