ADMV8502ACCZ-R7 datasheet(10/32 Pages) AD

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Data Sheet

ADMV8502

THEORY OF OPERATION

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CHIP ARCHITECTURE

The ADMV8502 contains several switched capacitors that allow

the RF performance to vary. A simplified diagram of the filter

architecture is shown in Figure 19.

Figure 19. Simplified Filter Architecture Diagram

The two center frequency capacitors (CFC) are configured by the

fCENTER load value, which manipulates the fCENTER of the filter.

Likewise, the bandwidth capacitor (CBW) is configured by the band-

width load value, which adjusts the bandwidth response of the

filter. Additionally, the two match capacitors (CMATCH) are set by the

match load value, which allows adjustments to impedance matching

of the filter.

The fCENTER, bandwidth, and match load values each have 256

states (8 bits). In theory, there are over 16 million possible states for

fCENTER, bandwidth, and match load values for each band within the

ADMV8502. To simplify selection of these values, Analog Devices

has developed three patent pending interpolation functions to ease

implementation.

RF CONNECTIONS

The RF1 and RF2 pins of the ADMV8502 are DC-coupled to

on-chip ESD protection diodes. If a DC voltage is present on the

RF1 and RF2 pins from other components within the system, it

is recommended to place DC blocking capacitors in series with

these pins. The DC blocking capacitors must be selected based

on the operating frequency of the filter. Generally, a value greater

than 10 nF is sufficient to minimize insertion loss at the lower

frequencies of operation. At higher frequencies of operation, it may

be necessary to consider the parasitic elements of the selected

capacitor. Figure 20 shows a general model of a capacitor with the

parasitic elements. The parasitic series inductance (LESL) is typical-

ly of most concern given that its impedance can become dominant.

The other parasitic elements, including the leakage resistance (RL),

the dielectric absorption resistance (RDA), the dielectric absorption

capacitance (CDA), and electrical series resistance (RESR) are less

critical elements for consideration but are shown in Figure 20 for

completeness.

Figure 20. Model of a Capacitor

SPI CONFIGURATION

The SPI of the ADMV8502 allows configuration of the device for

specific functions or operations via the 5-pin SPI port. This interface

provides users with added flexibility and customization. The SPI

consists of five control lines: SFL, SCLK, SDI, SDO, and CS. For

normal SPI operations, keep the SFL pin low.

The SPI protocol consists of an R/W bit followed by 15 register

address bits and 8 data bits. The address field and data field are

organized MSB first and end with the LSB.

Set the MSB to 0 for a write operation and set the MSB to 1 for a

read operation. The write cycle must be sampled on the rising edge

of SCLK. The 24 bits of the serial write address and data are shifted

in on the SDI control line, MSB to LSB. The ADMV8502 input logic

level for the write cycle supports a 3.3 V interface.

For a read cycle, the R/W bit and the 15 register address bits shift

in on the rising edge of SCLK on the SDI control line. Then, 8 bits of

serial read data shift out on the SDO control line, MSB first, on the

falling edge of SCLK. The output logic level for a read cycle is 3.3

V. The output drivers of the SDO are enabled after the last rising

edge of SCLK of the instruction cycle and remain active until the

end of the read cycle. In a read operation, when CS is deasserted,

SDO returns to high impedance until the next read transaction. CS

is active low and must be deasserted at the end of the write or read

sequence.

An active low input on CS starts and gates a communication

cycle. The CS pin allows more than one device to be used on the

same serial communications lines. The SDO pin goes to a high

impedance state when the CS input is high. During the communica-

tion cycle, the chip select must stay low. The SPI communications

protocol follows the Analog Devices SPI standard. For more infor-

mation, see the ADI-SPI Serial Control Interface Standard (Rev

1.0).

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