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MFS5600AMBAFES Datasheet(PDF) 35 Page - NXP Semiconductors

Part # MFS5600AMBAFES
Description  Automotive buck regulator and controller with voltage monitors and watchdog timer
PDF  118 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFS5600AMBAFES Datasheet(HTML) 35 Page - NXP Semiconductors

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NXP Semiconductors
FS5600
Automotive buck regulator and controller with voltage monitors and watchdog timer
14.3 Spread spectrum
The internal oscillator provides a programmable frequency spread spectrum to help manage EMC in automotive
applications. Spread spectrum is enabled by setting the FSS_EN bit. The initial value of FSS_EN is loaded from
OTP_FSS_EN and can be subsequently changed via I2C.
14.4 SW1 and SW2 switching frequency selection
The switching frequencies of SW1 and SW2 are derived from the 20 MHz clock. SW1 and SW2 use clock
pulses that are shifted by one 20 MHz clock period (50 ns) with respect to each other to allow interleaving of the
switching edges.
The 20 MHz clock is divided internally to form CLK1 and CLK2 as shown in the block diagram.
CLK1 uses a divide ratio of 8 if OTP_CLK1_DIV = 0 and a divide ratio of 9 if OTP_CLK1_DIV = 1.
CLK2 uses a divide ratio of 48 if OTP_CLK2_DIV = 0 and a divide ratio of 64 if OTP_CLK2_DIV = 1.
Using the OTP_SW1_CLKSEL and OTP_SW2_CLKSEL, switching frequency SW1 and SW2 regulators can be
assigned to either CLK1 or CLK2. Refer to the table below for the available combinations.
OTP_SW1/2_CLKSEL
selection
Switching frequency
OTP_SW1_CLKSEL = 0;
OTP_SW2_CLKSEL = 0;
Switching frequency
OTP_SW1_CLKSEL = 1;
OTP_SW2_CLKSEL = 1;
CLK1/CLK2 Selection
OTP_CLK1_DIV = 0
OTP_CLK1_
DIV = 1
OTP_CLK2_DIV = 0
OTP_CLK2_DIV = 1
SW1/SW2 Fsw at 16 MHz
clock
2.0000 MHz
1.7778 MHz
0.3333 MHz
0.25 MHz
SW1/SW2 Fsw at 17 MHz
clock
2.1250 MHz
1.8889 MHz
0.3542 MHz
0.265625 MHz
SW1/SW2 Fsw at 18 MHz
clock
2.2500 MHz
2.0000 MHz
0.3570 MHz
0.28125 MHz
SW1/SW2 Fsw at 19 MHz
clock
2.375 MHz
2.1111 MHz
0.3958 MHz
0.296875 MHz
SW1/SW2 Fsw at 20 MHz
clock
2.5000 MHz
2.2222 MHz
0.4167 MHz
0.3125 MHz
SW1/SW2 Fsw at 21 MHz
clock
2.6250 MHz
2.3333 MHz
0.4375 MHz
0.328125 MHz
SW1/SW2 Fsw at 22 MHz
clock
2.7500 MHz
2.4444 MHz
0.4583 MHz
0.34375 MHz
SW1/SW2 Fsw at 23 MHz
clock
2.8750 MHz
2.5556 MHz
0.4792 MHz
0.359375 MHz
SW1/SW2 Fsw at 24 MHz
clock
3.0000 MHz
2.6667 MHz
0.500 MHz
0.375 MHz
Table 29. SW1 and SW2 switching frequency selection
14.5 External clock synchronization
The MODE/SYNCIN pin can be configured as SYNCIN via OTP by setting OTP_MODE_SYNCINB = 0.
SYNCIN can be used to synchronize the FS5600 to an external clock source. The FS5600 can use either the
internal high frequency oscillator or the SYNCIN pin as its source based on the validity of the external clock.
FS5600
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 4 — 29 April 2024
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