MFS5600AMBAFES datasheet(55/118 Pages) NXP

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NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

When OTP_I2C_CRC_EN = 0, the CRC verification mechanism is disabled.

When OTP_I2C_CRC_EN = 1, the CRC verification mechanism is enabled.

After each I2C transaction, the device calculates the corresponding CRC byte to ensure the configuration

command has not been corrupted.

When a CRC fault is detected, the FS5600 ignores the erroneous configuration command and sets the CRC_I

bit.

The CRC_I is cleared by writing a 1 to it.

The FS5600 implements a CRC-8-SAE, per the SAE J1850 specification.

Polynomial = 0x11D

Initial value = 0xFF

Figure 18 shows the 8-bit CRC polynomial per SAE J1850.

aaa-028696

MSB Data

I2C CRS Polynominal

Seed: 1 1 1 1 1 1 1 1

Figure 18. 8-bit CRC Polynomial

17.9.2 NOT logic registers

To prevent unintended writes to critical registers, a required two-step writing process must be followed.

1. Write the desired data in the REGISTER

2. Write the NOT value of Step 1 to the corresponding NOT_REGISTER

For example,

• SWx regulator will be enabled if ((SWx_EN = 1 AND NOT_SWx_EN = 0) AND (ENx pin = HIGH)).

• SWx regulator will be disabled if ((SWx_EN = 0 AND NOT_SWx_EN = 1) OR (ENx pin = LOW)).

A real-time XOR is performed to ensure that only complimentary register values are accepted. Refer to

Section 18 for list of registers where this feature is applicable.

17.10 I2C write protection

To prevent unintended writes to critical registers during system NORMAL state, certain registers may be

modified only in the INIT_RUN state. These are:

FCCU12_BISTABLE

FCCU2_FLT_POL

FCCU1_FLT_POL

NOT_FCCU12_FLT_POL

NOT_FCCU12_BISTABLE

NOT_FCCU2_FLT_POL

NOT_FCCU1_FLT_POL

NOT_SW1_EN

SW1_EN

NOT_SW2_EN

SW2_EN

NOT_FLT_ERR_CNT_LIMIT[1:0]

Table 47. List of registers modifiable only during INIT_RUN state

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 29 April 2024

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