SST26VF016B-80ESLASHMF datasheet(6/84 Pages) MICROCHIP

6 / 84 page

SST26VF016B

DS20005262G-page 6



2014-2022 Microchip Technology Inc. and its subsidiaries

4.0

DEVICE OPERATION

SST26VF016B supports both Serial Peripheral Inter-

face (SPI) bus protocol and a 4-bit multiplexed SQI bus

protocol. To provide backward compatibility to tradi-

tional SPI Serial Flash devices, the device’s initial state

after a Power-on Reset is SPI mode which supports

multi-I/O (x1/x2/x4) Read/Write commands. A com-

mand instruction configures the device to SQI mode.

The dataflow in the SQI mode is similar to the SPI

mode, except it uses four multiplexed I/O signals for

command, address and data sequence.

SQI Flash Memory supports both Mode 0 (0,0) and

Mode 3 (1,1) bus operations. The difference between

the two modes is the state of the SCK signal when the

bus host is in standby mode and no data are being

transferred.

The SCK signal is low for Mode 0 and SCK signal is

high for Mode 3. For both modes, the Serial Data I/O

(SIO[3:0]) is sampled at the rising edge of the SCK

clock signal for input and driven after the falling edge of

the SCK clock signal for output. The traditional SPI pro-

tocol uses separate input (SI) and output (SO) data sig-

nals as shown in Figure 4-1. The SQI protocol uses

four multiplexed signals, SIO[3:0], for both data in and

data out, as shown in Figure 4-2. This means the SQI

protocol quadruples the traditional bus transfer speed

at the same clock frequency, without the need for more

pins on the package.

FIGURE 4-1:

SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)

FIGURE 4-2:

SQI SERIAL QUAD I/O PROTOCOL

4.1

Device Protection

SST26VF016B offers a flexible memory protection

scheme that allows the protection state of each individ-

ual block to be controlled separately. In addition, the

Write Protection Lock-Down register prevents any

change of the lock status during device operation. To

avoid inadvertent writes during power-up, the device is

write-protected by default after a Power-on Reset

cycle. A Global Block Protection Unlock command

offers a single command cycle that unlocks the entire

memory array for faster manufacturing throughput.

For extra protection, there is an additional nonvolatile

Protection register bits for each individual block.

Each of the corresponding lock-down bits are

One-Time-Programmable (OTP) — once written, they

cannot be erased. Data that had been previously pro-

grammed into these blocks cannot be altered by pro-

gramming or erase and are not reversible.

MODE 3

SCK

CE#

MODE 3

Don't Care

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

High-Impedance

MSb

MODE 3

CLK

SIO[3:0]

CE#

MODE 3

MODE 0

MSb

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