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SST79LF008 Datasheet(PDF) 29 Page - Silicon Storage Technology, Inc |
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SST79LF008 Datasheet(HTML) 29 Page - Silicon Storage Technology, Inc |
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29 / 252 page  Advance Information Mobile Platform Controller 8 Mbit LPC Firmware Flash SST79LF008 29 ©2006 Silicon Storage Technology, Inc. S71320-01-000 10/06 3.3 Data Memory Addressing Modes The Lower RAM is accessed by all 8051 instructions that utilize both direct and indirect internal data memory addressing modes. In addition the lowest 32 bytes (00H- 1FH) of Lower RAM are grouped into 4 banks of 8 regis- ters, which can be accessed by 8051 register addressing mode. Bytes 20H-2FH provide a 128-bit addressable space, accessible by 8051 bit addressing mode (bit addresses 00H-7FH). Because the Upper RAM occupies the same addresses as the SFRs, the respective data areas are distinguished by the type of addressing mode used: the Upper RAM is accessed via indirect internal data memory addressing mode, and the SFRs are accessed via direct internal data memory addressing mode. The SFRs that are located at addresses ended with 0H or 8H are also bit-addressable (bit addresses 80H-FFH). The entire Expanded RAM and MMCRs are accessed by 8051 MOVX instructions that utilize indirect external data memory addressing mode and DPTR pointer. Using MOVX with R0/R1 indirect pointer can only access the low- est 256 bytes of total 2KB Expanded RAM. The 8051 stack with default 8-bit addressing mode can be located anywhere within the 256 bytes of Lower and/or Upper RAM. For additional details on 8051 addressing modes refer to the description of standard 8051 instruction set. For the SST79LF008 enhanced 8051 MCU features, see Sec- tion 6.0. 3.4 Special Function Registers (SFRs) All Special Function Registers are located in 8051 internal data memory space, addresses 80H – FFH. For the detailed description of SFRs see the respective sections as specified in Tables 3-2, 3-3, 3-4, and 3-5. Some of SFRs contain reserved bits. On reads, software must not rely on reserved bits being any particular value. On writes, zeros should be written to reserved bits. When modifying a regis- ter with reserved bits the values read from the reserved bits can be written back to them. Software should not write to non used locations in SFR space. 3.4.1 SFR Map Function and bit definitions for registers ACC, B, PSW, and P1 are the same as in standard 8051 MCU. Registers P0, P2, P3 are reserved. For the detailed description of all other SFRs see the respective sections as specified in the reference charts below. TABLE 3-1: Special Function Register Memory Map 8 BYTES F8H IPA1 1. Bit addressable SFRs FFH F0H B1 IPAH F7H E8H IEA1 EFH E0H ACC1 E7H D8H DFH D0H PSW1 SPCR D7H C8H T2CON1 T2MOD RCAP2L RCAP2H TL2 TH2 CFH C0H C7H B8H IP1 SADEN BFH B0H P31 IPH B7H A8H IE1 SADDR SPSR EXIF CLKCON AFH A0H P21 AUXR1 A7H 98H SCON1 SBUF ESP ACON 9FH 90H P11 DPX 97H 88H TCON1 TMOD TL0 TL1 TH0 TH1 8FH 80H P01 SP DPL DPH SPDR PCON 87H T3-1.0 1320 |
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