SST79LF008 datasheet(45/252 Pages) SST

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Advance Information

Mobile Platform Controller

8 Mbit LPC Firmware Flash

SST79LF008

S71320-01-000

10/06

4.3 Shared ROM Interface

The SST79LF008 Shared ROM Interface (SRI) provides

LPC Host, alternate LPC (aLPC) Host and the 8051 MCU

with access to the entire 1 MByte of main Flash memory

array as well as to ENVR and UNVR areas. See Figure 4-2.

FIGURE

4-2: Shared ROM Interface

Both LPC and aLPC Hosts access flash memory via the

internal LPC bus interface unit (see details on switching

bus control between LPC Host and aLPC Host in Section

4.8). The aLPC Host flash access is exclusive as 8051 is

forced into reset state while aLPC mode is enabled. The

LPC Host and 8051 may access flash memory concur-

rently. For LPC Host read operations the arbitration

between LPC Host and 8051 is completely handled by SRI

hardware. For LPC Host program/erase operation flash

memory access arbitration must be implemented in soft-

ware via one of the following mechanisms:

1. 8051 firmware turns over the flash bus to the LPC

Host by setting HOST_ACCESS bit in SFCS reg-

ister, see Section 4.4.5, In this case 8051 firmware

must run from the Scratch ROM, described in

Section 4.4.1, just before and while the flash bus

is released to the LPC Host.

2. 8051 firmware enters Idle mode, which allows the

LPC Host software to take over the flash bus by

setting the STP_CLK bit in MBX94 register,

described in Section 21.2. In this case 8051 firm-

ware can run from flash before entering Idle mode

provided the LPC Host does not update the

respective flash locations.

For any mechanism above, the LPC Host software

can confirm the bus turn around by checking the

HOSTFLASH bit in MBX94 register. See Section

21.2.

3. 8051 firmware enables LPC Soft reset via LPC-

MON register, detailed in Section 23.1, which

allows the LPC Host to take over the flash bus by

sending a Force LPC Soft Reset command,

detailed in Section 7.3. In this case 8051 will be

kept in reset state and 8051 firmware will not run

until the LPC Host sends a Release LPC Soft

Reset command, which re-starts 8051 code exe-

cution. As KBC operation is aborted and then re-

started, this mechanism is not recommended for

LPC Host program/erase access, unless flash

memory is blank or corrupted.

1245 ShrdROM.0

LPC Bus

Host Interface

8051

Core

Shared-ROM

Interface

Flash Memory

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