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SST79LF008 Datasheet(PDF) 72 Page - Silicon Storage Technology, Inc

Part # SST79LF008
Description  Mobile Platform Controller plus 8 Mbit LPC Firmware Flash
PDF  252 Pages
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST79LF008 Datasheet(HTML) 72 Page - Silicon Storage Technology, Inc

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Advance Information
Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
©2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
5.3.2 Clock Selection Control and Clock Domains
The 8051 CPU and core peripherals clock (CCLK) are
derived from three different clock sources—the on-chip ring
oscillator (RCLK), the PLL clock (PCLK), and the external
clock source (ECLK). The 8051 can be programmed to
switch the clock source during normal code execution. The
8051 clock source can be selected through the Clock
Source Control Register (CLKSRCCON). In addition
peripheral modules Time0, Timer1, and PWM have their
own clock selection control registers described in Section
10.0. The 8051 core clock, as well as some peripheral
clocks, are stopped when 8051 enters either Idle mode or
Power Down mode. for PCON register description, see
Section 11.4.
FIGURE
5-4: SST79LF008 Clock Selection
The SST79LF008 clock usage and clock domains are summarized in the Table 5-4.
TABLE
5-4: Clock Domains for SST79LF008 Modules
MODULE
Clock Domain
Clock status in Idle mode
Clock status in Power Down
8051
8051 CPU clock
stop
stop
Timer 0/1
8051 core clock
run
stop
Peripheral clock
run
stop
Timer 2
8051 core clock
run
stop
Hibernation timer
Crystal Oscillator clock
run
run
WDT
Peripheral clock
run
run/stop depends on (WDTCSR[7])
Fan Tachometer
Peripheral clock
run
run/stop depends on
(FANTIMEBASE[7:6])
PWM
8051 core clock
run
stop
Crystal Oscillator clock
run
run
ADC
8051 core clock
run
stop
DAC
8051 core clock
run
stop
PWM LED
Crystal Oscillator clock
run
run
UART
8051 core clock
run
stop
SPI
8051 core clock
run
stop
SMBus
8051 core clock
run
stop
PS/2
8051 core clock
run
stop
GPIO
8051 core clock
run
stop (retain I/O state)
LPC Interface
LPC clock
X1
1. LPC clock status is controlled by the external LPC Host, it is not affected by 8051 Idle or Power Down mode.
X1
T5-4.1245
1245 ClockSel.0
EN
XTALEN
X'tal
PD
LCLK
ECLK
0
1
PD
XCLK
PD
PLLSTOP
EN
ROSCEN
RCLK
CLKSEL_8051
POWERGOOD
IDL
CCLK
MCLK
PCLK
Ring Oscillator
ST
PLL
Crystal Oscillator clock
Peripheral clock
LPC clock
8051 core clock
8051 CPU clock
0
1
Boundry internal to chip



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