TDA8366 datasheet(30/48 Pages) PHILIPS

30 / 48 page

January 1995

Philips Semiconductors

Objective speciﬁcation

I2C-bus controlled PAL/NTSC TV

processor

TDA8366

11. The AFC slope is directly related to the Q-factor of the demodulator tuned circuit. The given AFC steepness is

obtained with a Q-factor of 60. The AFC off-set is tested with a double sideband input signal and with the reference

tuned circuit tuned to minimum AGC voltage (optimum tuning for the demodulator).

The tuning information is supplied to the tuning system via the I2C-bus. Two bits have been reserved for this function.

The first bit indicates whether the tuning is within the given window. The second bit indicates the direction of the

tuning. Bit indications:

a) AFA = 1; tuning inside window.

b) AFA = 0; tuning outside window.

c) AFB = 1; tuning too high.

d) AFB = 0; tuning too low.

To improve the speed of search tuning systems the AFC window can be increased to about 240 kHz. The width of

the window can be set by means of the AFW bit in subaddress 03.

12. Signal with negative-going sync. Amplitude includes sync pulse amplitude.

13. This parameter is measured at nominal settings of the various controls.

14. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1).

15. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum

−10 dB. In the nominal

brightness setting the black level at the outputs is identical to the level of the black-current measuring pulses.

16. The

−3 dB bandwidth of the circuit can be calculated by means of the following equation:

17. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns

and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the

overshoots but by measuring the frequency response of the Y output.

18. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing

level and the black level (back porch).

19. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is

switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a

noise detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’

mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to

head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be

automatically or overruled by the I2C-bus.

The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be

used to close or open the first control loop when a video signal is present or not present on the input. This enables

a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification

circuit with the first loop can be defeated via the I2C-bus.

When the horizontal PLL is set to the ‘slow’ mode (via I2C-bus bits FOA and FOB) or during weak signal conditions

in the ‘automatic’ mode the phase detector is gated to obtain a good noise immunity. The width of the gating pulse

is 5.7

µs.

The output current of the phase detector in the various conditions are shown in Table 42.

20. During the start-up period of the oscillator the duty factor of the output pulse rises gradually from 0% to 50% (time

approximately 100 lines).

21. The start-up frequency depends on the SFM bit in the I2C-bus protocol. When SFM = 0 the frequency starts at a high

(non calibrated) value. When SFM = 1 the output signal will only be available after calibration.

3dB

–

osc 1

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–

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