AM79C940KCSLASHW datasheet(50/144 Pages) AMD

50 / 144 page

Am79C940

FIFO is controlled by the XMTFW bits in the FIFO Con-

figuration Control register. TDTREQ will be asserted

when one of the following conditions is true:

s The number of bytes free in the Transmit FIFO rel-

ative to the current Saved Read Pointer value is

greater than or equal to the threshold set by the

XMTFW (16, 32 or 64 bytes). The Saved Read

Pointer is the first byte of the current transmit frame,

either in progress or awaiting channel availability.

s The number of bytes free in the Transmit FIFO rel-

ative to the current Read Pointer value is greater

than or equal to the threshold set by the XMTFW

(16, 32 or 64 bytes). The Read Pointer becomes

available only after a minimum of 64 byte frame

length has been transmitted on the network (eight

bytes of preamble plus 56 bytes of data), and points

to the current byte of the frame being transmitted.

Depending on the bus latency of the system, XMTFW

can be set to ensure that the Transmit FIFO does not

underflow before more data is written into the FIFO.

When the entire frame is in the FIFO, TDTREQ will

remain asserted if sufficient bytes remain empty. The

default value of XMTFW is 64 bytes after hardware or

software reset. Note that if the XMTFW is set below the

64 byte limit, the transmit latency for the host to service

the MACE device is effectively increased, since

TDTREQ will occur earlier in the transmit sequence

and more bytes will be present in the Transmit FIFO

when the TDTREQ is de-asserted.

The transmit operation of the MACE device can be

halted at any time by clearing the ENXMT bit (bit 1) in

the MAC Configuration Control register. Note that any

complete transmit frame that is in the Transmit FIFO

and is currently in progress will complete, prior to the

transmit function halting. Transmit frames in the FIFO

which have not commenced will not be started. Trans-

mit frames which have commenced but which have not

been fully transferred into the Transmit FIFO will be

aborted, in one of two ways. If less than 544 bits

(68 bytes) have been transmitted onto the network, the

transmission will be terminated immediately, generat-

ing a runt packet which can be deleted at the receiving

station. If greater than 544 bits have been transmitted,

the messages will have the current CRC inverted and

appended at the next byte boundary, to guarantee an

error is detected at the receiving station. This feature

ensures that packets will not be generated with poten-

tial undetected data corruption. An explanation of the

544 bit derivation appears in the “Automatic Pad

Generation” section.

Automatic Pad Generation

Transmit frames can be automatically padded to ex-

tend them to 64 data bytes (excluding preamble) per-

mitting the minimum frame size of 64 bytes (512 bits)

for 802.3/Ethernet to be guaranteed, with no software

intervention from the host system.

APAD XMT = 1 enables the automatic padding feature.

The pad is placed between the LLC Data field and FCS

field in the 802.3 frame. The FCS is always added if

APAD XMT = 1, regardless of the state of DXMTFCS.

The transmit frame will be padded by bytes with the

value of 00h. The default value of APAD XMT will

enable auto pad generation after hardware or software

reset.

It is the responsibility of upper layer software to cor-

rectly define the actual length field contained in the

message to correspond to the total number of LLC

Data bytes encapsulated in the packet (length field as

defined in the IEEE 802.3 standard). The length value

contained in the message is not used by the MACE

device to compute the actual number of pad bytes to be

inserted. The MACE chip will append pad bytes depen-

dent on the actual number of bits transmitted onto the

network. Once the last data byte of the frame has com-

pleted, prior to appending the FCS, the MACE device

will check to ensure that 544 bits have been transmit-

ted. If not, pad bytes are added to extend the frame

size to this value, and the FCS is then added.

The 544 bit count is derived from the following:

Preamble

1010....1010

SFD

10101011

Dest

Addr

Srce

Addr

Length

LLC

Data

Pad

FCS

Bits

Bytes

46—1500

Bytes

IEEE 802.3 Format Data Frame

16235D-7

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