DS3101 datasheet(21/149 Pages) DALLAS

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DS3101 Stratum 3/3E Timing Card IC

21 of 149

Table 7-2. Input Clock Capabilities

INPUT

CLOCK

SIGNAL

FORMATS

FREQUENCIES

DEFAULT FREQUENCY

IC1

AMI or

CMOS/TTL

(3)

64kHz composite clock or up

to 125MHz

8kHz

IC2

AMI or

CMOS/TTL

(3)

64kHz composite clock or up

to 125MHz

8kHz

IC3

CMOS/TTL

Up to 125MHz

(1)

8kHz

IC4

CMOS/TTL

Up to 125MHz

8kHz

IC5

LVDS/LVPECL

or CMOS/TTL

Up to 155.52MHz

(2)

19.44MHz

IC6

LVDS/LVPECL

or CMOS/TTL

Up to 155.52MHz

19.44MHz

IC7

CMOS/TTL

Up to 125MHz

19.44MHz

IC8

CMOS/TTL

Up to 125MHz

19.44MHz

IC9

CMOS/TTL

Up to 125MHz

19.44MHz

IC10

CMOS/TTL

Up to 125MHz

19.44MHz

IC11

CMOS/TTL

Up to 125MHz

Master mode (MASTSLV = 1): 19.44MHz

Slave mode (MASTSLV = 0): 6.48MHz

IC12

CMOS/TTL

Up to 125MHz

SONET mode (SONSDH = 1): 1.544MHz

SDH mode (SONSDH = 0): 2.048MHz

IC13

CMOS/TTL

Up to 125MHz

SONET mode (SONSDH = 1): 1.544MHz

SDH mode (SONSDH = 0): 2.048MHz

IC14

CMOS/TTL

Up to 125MHz

SONET mode (SONSDH = 1): 1.544MHz

SDH mode (SONSDH = 0): 2.048MHz

Note 1:

Available frequencies for CMOS/TTL input clocks are 2kHz, 4kHz, 8kHz, 1.544MHz (SONET mode), 2.048MHz (SDH mode),

6.312MHz, 6.48MHz, 19.44MHz, 25.92MHz, 38.88MHz, 51.84MHz, 77.76MHz, and N x 8kHz for 2

≤ N ≤ 15,625.

Note 2:

Available frequencies for LVDS/LVPECL input clocks include all CMOS/TTL frequencies in Note 1 plus 155.52MHz.

Note 3:

Signal formats for IC1 and IC2 are controlled by MCR5:IC1SF and IC2SF, respectively.

DS3101 Datasheet(PDF) 21 Page - Dallas Semiconductor

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