DS3101 datasheet(39/149 Pages) DALLAS

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DS3101 Stratum 3/3E Timing Card IC

39 of 149

7.8.1

Signal Format Configuration

Output clocks OC6 and OC7 are enabled and disabled via the OC6SF and OC7SF configuration bits in the MCR8

shown in Figure 10-1. These outputs can be easily interfaced to LVPECL and CML inputs on neighboring ICs using

a few external passive components. Refer to Maxim App Note HFAN-1.0: Introduction to LVDS, PECL, and CML

for details.

Output clock OC8 is a dedicated composite clock (CC) transmitter. The composite clock signal is a 64kHz AMI

clock with an embedded 8kHz clock indicated by deliberate bipolar violations (BPVs) every 8 clock cycles. See

Section 7.10.2 for OC8 configuration details. The AMI CC electrical specifications are shown in Table 10-6, and the

recommended external components are shown in Figure 10-3.

Output clocks OC1 to OC5 and OC9 to OC11 are always CMOS/TTL signal format.

7.8.2

Frequency Configuration

The frequency of most of the output clocks is a function of the settings used to configure the components of the T0

and T4 PLL paths. These components are shown in the detailed block diagram of Figure 7-5.

The T0 and T4 PLLs use digital frequency synthesis (DFS) to generate various clocks. In DFS, a high-speed

master clock (204.8MHz) is divided down to the desired output frequency. The edges of the output clock, however,

are not ideally located in time but rather are aligned with the edges of the master clock resulting in jitter with an

amplitude equal to 1 period of the master clock (i.e., 4.88ns).

7.8.2.1

T0 DPLL and APLL Details

The 77M forward DFS block (see Figure 7-5) uses the 204.8MHz master clock and DFS to synthesize a 77.76MHz

clock with 4.88ns inherent peak-to-peak jitter. This clock can be fed directly to the feedback DFS block or it can be

passed through the feedback APLL to reduce jitter to less than 1ns. The 77M forward DFS block handles phase

build-out and any phase offset configured in the OFFSET registers. Thus, the 77M output DFS block and the 77M

forward DFS block are frequency locked but may have a phase offset.

The feedback DFS block takes as its input clock either the output from the 77M forward DFS or the jitter-filtered

output from the T0 feedback APLL. The feedback DFS block synthesizes the appropriate locking frequency for use

in the phase-frequency detector (PFD).

The 77M output DFS block also uses the 204.8MHz master clock and DFS to synthesize a 77.76MHz clock with

4.88ns peak-to-peak jitter. This clock goes to both the output APLL and the low frequency (LF) output DFS block.

DS3101 Datasheet(PDF) 39 Page - Dallas Semiconductor