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PIC16F688-E/ST Datasheet(PDF) 77 Page - Microchip Technology |
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PIC16F688-E/ST Datasheet(HTML) 77 Page - Microchip Technology |
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77 / 174 page  2004 Microchip Technology Inc. Preliminary DS41203B-page 75 PIC16F688 FIGURE 9-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION TABLE 9-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM Addr Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0 Value on POR, BOD Value on all other Resets 0Bh/8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000 0Ch PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000 8Ch PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000 97h EEDATH EEPROM Data register, high byte --00 0000 0000 0000 98h EEADRH EEPROM Address register, high byte ---- 0000 0000 0000 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 9Ch EECON1 EEPGD — — — WRERR WREN WR RD ---- x000 ---- q000 9Dh EECON2(1) — — — — — — — —— — Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by data EEPROM module. Note 1: EECON2 is not a physical register. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 BSF EECON1,RD executed here INSTR(PC+1) executed here Forced NOP executed here PC PC+1 EEADRH,EEADR PC+3 PC+5 Flash ADDR RD bit EEDATH,EEDAT PC+3 PC+4 INSTR (PC+1) INSTR(PC-1) executed here INSTR(PC+3) executed here INSTR(PC+4) executed here Flash Data EEDATH EEDAT Register EERHLT INSTR (PC) INSTR (PC+3) INSTR (PC+4) |
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