DSPIC33FJ32GP202-ESLASHML datasheet(89/252 Pages) MICROCHIP

89 / 252 page

Preliminary

DS70290A-page 87

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

6.4

Interrupt Setup Procedures

6.4.1

INITIALIZATION

To configure an interrupt source at initialization:

Set the NSTDIS bit (INTCON1<15>) if nested

interrupts are not desired.

Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx register. The priority level will

depend on the specific application and type of

interrupt source. If multiple priority levels are not

desired, the IPCx register control bits for all

enabled interrupt sources can be programmed

to the same non-zero value.

Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx register.

Enable the interrupt source by setting the

interrupt enable control bit associated with the

source in the appropriate IECx register.

6.4.2

INTERRUPT SERVICE ROUTINE

The method used to declare an ISR and initialize the

IVT with the correct vector address depends on the

programming language (C or Assembler) and the lan-

guage development toolsuite used to develop the appli-

cation.

In general, the user application must clear the interrupt

flag in the appropriate IFSx register for the source of

interrupt that the ISR handles. Otherwise, the program

will re-enter the ISR immediately after exiting the

routine. If the ISR is coded in assembly language, it

must be terminated using a RETFIE instruction to

unstack the saved PC value, SRL value and old CPU

priority level.

6.4.3

TRAP SERVICE ROUTINE

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

6.4.4

INTERRUPT DISABLE

All user interrupts can be disabled using this proce-

dure:

Push the current SR value onto the software

stack using the PUSH instruction.

Force the CPU to priority level 7 by inclusive

ORing the value OEh with SRL.

To enable user interrupts, the POP instruction can be

used to restore the previous SR value.

The DISI instruction provides a convenient way to dis-

able interrupts of priority levels 1-6 for a fixed period of

time. Level 7 interrupt sources are not disabled by the

DISI instruction.

Note:

At a device Reset, the IPCx registers are

initialized such that all user interrupt

sources are assigned to priority level 4.

Note:

Only user interrupts with a priority level of

7 or lower can be disabled. Trap sources

(level 8-level 15) cannot be disabled.

DSPIC33FJ32GP202-E/ML Datasheet(PDF) 89 Page - Microchip Technology

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