DSPIC33FJ32GP202-ESLASHML datasheet(102/252 Pages) MICROCHIP

102 / 252 page

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

DS70290A-page 100

Preliminary

8.2.2

IDLE MODE

The following occur in Idle mode:

• The CPU stops executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 8.4

“Peripheral Module Disable”).

• If the WDT or FSCM is enabled, the LPRC also

remains active.

The device will wake from Idle mode on any of these

events:

• Any interrupt that is individually enabled.

• Any device Reset

• A WDT time-out

On wake-up from Idle mode, the clock is reapplied to

the CPU and instruction execution begins immediately,

starting with the instruction following the PWRSAV

instruction, or the first instruction in the ISR.

8.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a

PWRSAV instruction is held off until entry into Sleep or

Idle mode has completed. The device then wakes up

from Sleep or Idle mode.

8.3

Doze Mode

The preferred strategies for reducing power consump-

tion are changing clock speed and invoking one of the

power-saving modes. In some circumstances, however,

these are not practical. For example, it may be neces-

sary for an application to maintain uninterrupted syn-

chronous communication, even while it is doing nothing

else. Reducing system clock speed can introduce com-

munication errors, while using a power-saving mode can

stop communications completely.

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock contin-

ues to operate from the same source and at the same

speed. Peripheral modules continue to be clocked at

the same speed, while the CPU clock speed is

reduced. Synchronization between the two clock

domains is maintained, allowing the peripherals to

access the SFRs while the CPU executes code at a

slower rate.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>).

There

are

eight

possible

configurations, from 1:1 to 1:128, with 1:1 being the

default setting.

Programs can use Doze mode to selectively reduce

power consumption in event-driven applications. This

allows clock-sensitive functions, such as synchronous

communications, to continue without interruption while

the CPU idles, waiting for something to invoke an inter-

rupt routine. An automatic return to full-speed CPU

operation on interrupts can be enabled by setting the

ROI bit (CLKDIV<15>). By default, interrupt events

have no effect on Doze mode operation.

For example, suppose the device is operating at

20 MIPS and the CAN module has been configured for

500 kbps based on this device operating speed. If the

device is placed in Doze mode with a clock frequency

ratio of 1:4, the CAN module continues to communicate

at the required bit rate of 500 kbps, but the CPU now

starts executing instructions at a frequency of 5 MIPS.

8.4

Peripheral Module Disable

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a peripheral is disabled using the appropriate

PMD control bit, the peripheral is in a minimum power

consumption state. The control and status registers

associated with the peripheral are also disabled, so

writes to those registers will have no effect and read

values will be invalid.

A peripheral module is enabled only if both the associ-

ated bit in the PMD register is cleared and the peripheral

is supported by the specific dsPIC® DSC variant. If the

peripheral is present in the device, it is enabled in the

PMD register by default.

Note:

If a PMD bit is set, the corresponding mod-

ule is disabled after a delay of one instruc-

tion cycle. Similarly, if a PMD bit is cleared,

the corresponding module is enabled after

a delay of one instruction cycle (assuming

the module control registers are already

configured to enable module operation).

DSPIC33FJ32GP202-E/ML Datasheet(PDF) 102 Page - Microchip Technology

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