PIC18F258-ESLASHLSQTP datasheet(239/402 Pages) MICROCHIP

239 / 402 page

DS41159E-page 237

PIC18FXX8

19.12 Error Detection

The CAN protocol provides sophisticated error detection

mechanisms. The following errors can be detected.

19.12.1

CRC ERROR

With the Cyclic Redundancy Check (CRC), the

transmitter calculates special check bits for the bit

sequence, from the start of a frame until the end of the

data field. This CRC sequence is transmitted in the

CRC field. The receiving node also calculates the CRC

sequence using the same formula and performs a

comparison to the received sequence. If a mismatch is

detected, a CRC error has occurred and an error frame

is generated. The message is repeated.

19.12.2

ACKNOWLEDGE ERROR

In the Acknowledge field of a message, the transmitter

checks if the Acknowledge slot (which was sent out as

a recessive bit) contains a dominant bit. If not, no other

node has received the frame correctly. An Acknowl-

edge Error has occurred; an error frame is generated

and the message will have to be repeated.

19.12.3

FORM ERROR

If a node detects a dominant bit in one of the four

segments, including end of frame, interframe space,

Acknowledge delimiter or CRC delimiter, then a Form

Error has occurred and an error frame is generated.

The message is repeated.

19.12.4

BIT ERROR

A Bit Error occurs if a transmitter sends a dominant bit

and detects a recessive bit, or if it sends a recessive bit

and detects a dominant bit, when monitoring the actual

bus level and comparing it to the just transmitted bit. In

the case where the transmitter sends a recessive bit

and a dominant bit is detected during the arbitration

field and the Acknowledge slot, no Bit Error is

generated because normal arbitration is occurring.

19.12.5

STUFF BIT ERROR

If, between the start of frame and the CRC delimiter, six

consecutive bits with the same polarity are detected,

the bit stuffing rule has been violated. A Stuff Bit Error

occurs and an error frame is generated. The message

is repeated.

19.12.6

ERROR STATES

Detected errors are made public to all other nodes via

error frames. The transmission of the erroneous

message is aborted and the frame is repeated as soon

as possible. Furthermore, each CAN node is in one of

the three error states “error-active”, “error-passive” or

“bus-off” according to the value of the internal error

counters. The error-active state is the usual state,

where the bus node can transmit messages and

activate error frames (made of dominant bits) without

any restrictions. In the error-passive state, messages

and passive error frames (made of recessive bits) may

be transmitted. The bus-off state makes it temporarily

impossible for the station to participate in the bus

communication. During this state, messages can

neither be received nor transmitted.

19.12.7

ERROR MODES AND ERROR

COUNTERS

The PIC18FXX8 contains two error counters: the

Receive Error Counter (RXERRCNT) and the Transmit

Error Counter (TXERRCNT). The values of both

counters can be read by the MCU. These counters are

incremented or decremented in accordance with the

CAN bus specification.

The PIC18FXX8 is error-active if both error counters

are below the error-passive limit of 128. It is error-

passive if at least one of the error counters equals or

exceeds 128. It goes to bus-off if the transmit error

counter equals or exceeds the bus-off limit of 256. The

device remains in this state until the bus-off recovery

sequence is received. The bus-off recovery sequence

consists of 128 occurrences of 11 consecutive

recessive bits (see Figure 19-10). Note that the CAN

module, after going bus-off, will recover back to error-

active without any intervention by the MCU if the bus

remains Idle for 128 x 11 bit times. If this is not desired,

the error Interrupt Service Routine should address this.

The current error mode of the CAN module can be read

by the MCU via the COMSTAT register.

Additionally, there is an Error State Warning flag bit,

EWARN, which is set if at least one of the error

counters equals or exceeds the error warning limit of

96. EWARN is reset if both error counters are less than

the error warning limit.

PIC18F258-E/LSQTP Datasheet(PDF) 239 Page - Microchip Technology

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