UMA1015MSLASHC2 datasheet(10/24 Pages) PHILIPS

10 / 24 page

1995 Jun 22

Philips Semiconductors

Product speciﬁcation

Low-power dual frequency synthesizer

for radio communications

UMA1015M

SERIAL TIMING CHARACTERISTICS

VDD1 =3V; Tamb =25 °C unless otherwise speciﬁed.

Logic input signal levels; DATA, CLK, E and HPD

VIH

HIGH level input voltage

at logic 1

0.7VDD1

−

VDD1 + 0.3

VIL

LOW level input voltage

at logic 0

−0.3

−

0.3VDD1

Ibias

input bias currents

at logic 1 or logic 0

−5

−

µA

input capacitance

indicative, not tested

−

Port outputs/Out-of-lock; P0/OOL, P1, P2, P3 and fXTALO - open drain outputs

VOL

LOW level output voltage

Isink = 0.4 mA

−−

0.4

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Serial programming clock; CLK

tr, tf

input rise and fall times

−

tcy

clock period

100

−−

Enable programming; E

tSTART

delay to rising clock edge

−−

tEND

delay from last falling clock edge

−20

−−

minimum inactive pulse width

4000

−−

tSU;E

enable set-up time to next clock edge

−−

tSU;DAT

input data to clock set-up time

−−

tHD;DAT

input data to clock hold time

−−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Fig.3 Serial bus timing diagram.

UMA1015M/C2 Datasheet(PDF) 10 Page - NXP Semiconductors

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