CS44800_06 datasheet(70/80 Pages) CIRRUS

70 / 80 page

DS632F1

CS44800

state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” on

page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.30.2

Minimum PWM Output Pulse Settings (MIN_PULSE[4:0])

Default = 00000

Function:

The PWM Minimum Pulse registers allow settings for the minimum allowable pulse width on each of the

PWMOUT differential signal pairs, PWMOUTxx+ and PWMOUTxx-. The value selected in this register is

applicable to all PWM channels. The effective minimum pulse is calculated by multiplying the register val-

ue by the period of the PWM_MCLK. This parameter can only be changed when all modulators and as-

sociated logic are in the power-down state by setting the PDN bit in the register “Clock Configuration and

Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set

will be ignored.

7.31

PWMOUT Delay Register (address 33h)

7.31.1

Differential Signal Delay (DIFF_DLY[2:0])

Default = 000

Function:

The Differential Signal Delay bits allow delay adjustment between each channel’s differential signals,

PWMOUTxx+ and PWMOUTxx-. This set of bits control the delay between PWMOUTxx+ and PW-

MOUTxx- across all active channels. The value of this register determines the amount of delay inserted

in the output path. The effective delay is calculated by multiplying the register value by the period of the

PWM_MCLK. This parameter can only be changed when all modulators and associated logic are in the

power-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address

02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.31.2

Channel Delay Settings (CHNL_DLY[4:0])

Default = 00000

Function:

Binary Code

MIN_PULSE[4:0]

Minimum Pulse

Setting (multiply by

PWM_MCLK period)

00000

0 - no minimum

00110

10100

11111

Table 14. PWM Minimum Pulse Width Settings

DIFF_DLY2

DIFF_DLY1

DIFF_DLY0

CHNL_DLY4

CHNL_DLY3

CHNL_DLY2

CHNL_DLY1

CHNL_DLY0

Binary Code

Delay Setting (multiply by

PWM_MCLK period)

000

0 - no delay

001

100

111

Table 15. Differential Signal Delay Settings

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