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CS44800 Datasheet(PDF) 15 Page - Cirrus Logic |
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CS44800 Datasheet(HTML) 15 Page - Cirrus Logic |
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15 / 80 page  DS632F1 15 CS44800 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (VD = 2.5 V, VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL =30pF) 19. Data must be held for sufficient time to bridge the transition time of CCLK. 20. For fsck <1 MHz. Parameter Symbol Min Typ Max Units CCLK Clock Frequency fsck 0- 6.0 MHz CS High Time between Transmissions tcsh 1.0 - - µs CS Falling to CCLK Edge tcss 20 - - ns CCLK Low Time tscl 66 - - ns CCLK High Time tsch 66 - - ns CDIN to CCLK Rising Setup Time tdsu 40 - - ns CCLK Rising to DATA Hold Time (Note 19) tdh 15 - - ns CCLK Falling to CDOUT Stable tpd - - 50 ns Rise Time of CDOUT tr1 - - 25 ns Fall Time of CDOUT tf1 - - 25 ns Rise Time of CCLK and CDIN (Note 20) tr2 - - 100 ns Fall Time of CCLK and CDIN (Note 20) tf2 - - 100 ns t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN t css t pd CDOUT t csh Figure 9. Control Port Timing - SPI Format |
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