Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

CS44800 Datasheet(PDF) 30 Page - Cirrus Logic

Part # CS44800
Description  8-Channel Digital Amplifier Controller
PDF  80 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS44800 Datasheet(HTML) 30 Page - Cirrus Logic

Back Button CS44800_06 Datasheet HTML 26Page - Cirrus Logic CS44800_06 Datasheet HTML 27Page - Cirrus Logic CS44800_06 Datasheet HTML 28Page - Cirrus Logic CS44800_06 Datasheet HTML 29Page - Cirrus Logic CS44800_06 Datasheet HTML 30Page - Cirrus Logic CS44800_06 Datasheet HTML 31Page - Cirrus Logic CS44800_06 Datasheet HTML 32Page - Cirrus Logic CS44800_06 Datasheet HTML 33Page - Cirrus Logic CS44800_06 Datasheet HTML 34Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 30 / 80 page
background image
30
DS632F1
CS44800
4.4.1.5
One Line Mode #2
In One Line mode #2 format, data is received most significant bit first on the first DAI_SCLK after a
DAI_LRCK transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 256 Fs
rate. DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sam-
pled as valid on the same clock edge as the most significant bit of the first data sample and must be held
high for 128 DAI_SCLK periods. Each time slot is 24 bits wide, with the valid data sample left-justified with-
in the time slot. Valid data lengths are 16, 18, 20, or 24 bits. Valid samples rates for this mode are 32 kHz
to 96 kHz.
4.4.1.6
TDM Mode
In TDM mode format, data is received most significant bit first on the first DAI_SCLK after a DAI_LRCK
transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 256 Fs rate.
DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sampled
as valid on the proceeding clock edge as the most significant bit of the first data sample and must be held
valid for at least 1 DAI_SCLK period. Each time slot is 32 bits wide, with the valid data sample left-justified
within the time slot. Valid data lengths are 16, 18, 20, 24 or 32 bits. Valid samples rates for this mode are
32 kHz to 96 kHz.
PWMOUTB3
DAI_LRCK
DAI_SCLK
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
MSB
DAI_SDIN4
DAI_SDIN1
PWMOUTA1
PWMOUTB1
PWMOUTA2
PWMOUTB2
PWMOUTA3
LSB
MSB
LSB
MSB
PWMOUTA4
PWMOUTB4
MSB
128 clks
128 clks
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
Left Channels
Right Channels
Figure 21. One Line Mode #2 Serial Audio Format
PWMOUTB2
DAI_LRCK
DAI_SCLK
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
DAI_SDIN1
PWMOUTA1
PWMOUTA2
PWMOUTB1
PWMOUTA3
256 clks
32 clks
32 clks
32 clks
32 clks
32 clks
LSB
MSB
PWMOUTB3
32 clks
LSB
MSB
PWMOUTA4
32 clks
LSB
MSB
PWMOUTB4
32 clks
LSB
Figure 22. TDM Mode Serial Audio Format



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com