AS7C31026C datasheet(1/10 Pages) ALSC

Part #	AS7C31026C

Description	3.3 V 64K X 16 CMOS SRAM

PDF	10 Pages

Scroll/Zoom	100%

Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

Logo

1 / 10 page

September 2006

Advance Information

AS7C31026C

3.3 V 64K X 16 CMOS SRAM

9/20/06, v 1.0

Alliance Memory

P. 1 of 10

®

Features

• Industrial (-40o to 85oC) temperature

• Organization: 65,536 words × 16 bits

• Center power and ground pins for low noise

• High speed

- 10 ns address access time

- 5 ns output enable access time

• Low power consumption via chip deselect

• Upper and Lower byte pin

• Easy memory expansion with CE, OE inputs

• TTL-compatible, three-state I/O

• JEDEC standard packaging

- 44-pin 400 mil SOJ

- 44-pin TSOP 2-400

- 48-ball 6 × 8 mm BGA

• ESD protection

≥ 2000 volts

Logic block diagram

65,536 × 16

Array

OE

CE

WE

Address decoder

A0

A1

A2

A3

A4

A5

A7

VCC

GND

Control circuit

I/O0–I/O7

I/O8–I/O15

UB

LB

I/O

buffer

A6

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

I/O13

I/O12

GND

VCC

I/O11

I/O10

I/O9

I/O8

NC

A8

A9

A10

A11

NC

A0

CE

I/O0

I/O1

I/O2

I/O3

VCC

GND

I/O4

I/O5

I/O6

I/O7

WE

A15

A14

A13

44-Pin SOJ (400 mil), TSOP 2

21

22

A12

NC

UB

LB

I/O15

I/O14

2

A3

3

A2

4

A1

1

A4

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

43

42

41

44

A6

A7

OE

A5

Pin arrangement

0000048 - BGA Ball-Grid-Array Package

12

3

4

5

6

ALB

OE

A0

A1

A2

NC

BI/O8

UB

A3

A4

CE

I/O0

CI/O9

I/O10

A5

A6

I/O1

I/O2

DVSS I/O11 NC

A7

I/O3 VDD

EVDD I/O12 NC

NC

I/O4

VSS

FI/O14 I/O13 A14

A15 I/O5

I/O6

G I/O15

NC

A12

A13 WE

I/O7

HNC

A8

A9A10 A11

NC

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