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ST72324BJ2 Datasheet(PDF) 61 Page - STMicroelectronics |
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ST72324BJ2 Datasheet(HTML) 61 Page - STMicroelectronics |
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61 / 188 page  ST72324B On-chip peripherals 61/188 Figure 32. Watchdog block diagram 10.1.4 How to program the Watchdog timeout Figure 33 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If more precision is needed, use the formulae in Figure 34. Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 33. Approximate timeout duration Reset WDGA 6-bit downcounter (CNT) fOSC2 T6 T0 WDG prescaler Watchdog Control register (WDGCR) div 4 T1 T2 T3 T4 T5 12-bit MCC RTC counter LSB Div 64 0 5 6 11 MCC/RTC TB[1:0] bits (MCCSR register) MSB Watchdog timeout (ms) @ 8 MHz. fOSC2 3F 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114 |
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