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ST72324BJ2 Datasheet(PDF) 144 Page - STMicroelectronics |
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ST72324BJ2 Datasheet(HTML) 144 Page - STMicroelectronics |
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144 / 188 page ![]() Electrical characteristics ST72324B 144/188 12.6 Clock and timing characteristics Subject to general operating conditions for VDD, fCPU, and TA. 12.6.1 General timings 12.6.2 External clock source Figure 65. Typical application with an external clock source Table 92. General timings Symbol Parameter Conditions Min Typ(1) 1. Data based on typical application software. Max Unit tc(INST) Instruction cycle time 23 12 tCPU fCPU = 8 MHz 250 375 1500 ns tv(IT) Interrupt reaction time tv(IT) = ∆tc(INST) + 10 (2) 2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 10 22 tCPU fCPU =8MHz 1.25 2.75 µs Table 93. External clock source Symbol Parameter Conditions Min Typ Max Unit VOSC1H OSC1 input pin high level voltage See Figure 65. VDD-1 VDD V VOSC1L OSC1 input pin low level voltage VSS VSS+1 tw(OSC1H) tw(OSC1L) OSC1 high or low time(1) 1. Data based on design simulation and/or technology characteristics, not tested in production. 5 ns tr(OSC1) tf(OSC1) OSC1 rise or fall time(1) 15 Ilkg OSC1 input leakage current VSS < VIN < VDD ±1 µA OSC1 OSC2 fOSC External ST72XXX clock source Not connected internally VOSC1L VOSC1H tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L) Ilkg 90% 10% |
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