PPC440SP-RNC533C datasheet(14/85 Pages) AMCC

14 / 85 page

PowerPC 440SP Embedded Processor

AMCC Proprietary

Revision 1.23 - Sept 26, 2006

Data Sheet

Features include:

• Two IIC interfaces provided

• Support for Philips‚ Semiconductors I2C Specification, dated 1995

• Operation at 100kHz or 400kHz

•8-bit data

• 10- or 7-bit address

• Slave transmitter and receiver

• Master transmitter and receiver

• Multiple bus masters

• Supports fixed VDD IIC interface

• Two independent 4 x 1 byte data buffers

• Twelve memory-mapped, fully programmable configuration registers

• One programmable interrupt request signal

• Full management of all IIC bus protocols

• Programmable error recovery

• Port 0 supports serial Bootstrap ROM with default parameters override at initialization

General Purpose Timers (GPT)

Provides a time base counter and system timers additional to those defined in the processor core.

• 32-bit time base counter driven by the OPB bus clock

• Seven 32-bit compare timers

General Purpose IO (GPIO) Controller

• Controller functions and GPIO registers are programmed and accessed by means of memory-mapped OPB

bus master accesses.

• The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO

capabilities acts as a GPIO or is used for another purpose.

• Each GPIO output is a separately programmable tri-state driver (pull-up, pull-down, or open-drain).

PPC440SP-RNC533C Datasheet(PDF) 14 Page - Applied Micro Circuits Corporation