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PPC440SP-RNC533C Datasheet(PDF) 82 Page - Applied Micro Circuits Corporation |
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PPC440SP-RNC533C Datasheet(HTML) 82 Page - Applied Micro Circuits Corporation |
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82 / 85 page ![]() PowerPC 440SP Embedded Processor 82 AMCC Proprietary Revision 1.23 - Sept 26, 2006 Data Sheet The following figure shows the timing relationship between SDRAM DDR Data at the input pin and the store of the data in stage 1. Figure 11. DDR SDRAM Read Cycle Timing Example DQS at PLB 1X Clock Data at pin D0 D2 High Low FeedBack D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Data out Stage 2 D1 D3 DDR 1X Clock DDR 2X Clock Memclk (Diff.) Data out Stage 1 (0) Delayed DQS Data out Stage 1 (2) Data out Stage 1 (1) output 1X DDR Clk cycle MemCntl pin Oversampling Guard Band Valid Store 1st Data in Stage 2 T1 T2 T3 T4 |
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