LIS202DL datasheet(11/36 Pages) STMICROELECTRONICS

11 / 36 page

LIS202DL

Application hints

11/36

Application hints

Figure 3.

LIS202DL electrical connection

The device core is supplied through Vdd line while the I/O pads are supplied through

Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10

µF Al) should be

placed as near as possible to the pin 6 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper

behavior of the IC (Figure 3: LIS202DL electrical connection). It is possible to remove Vdd

maintaining Vdd_IO without blocking the communication busses, in this condition the

measurement chain is powered off.

The functionality of the device and the measured acceleration data is selectable and

accessible through the I2C/SPI interface.When using the I2C, CS must be tied high while

SDO must be left floating.

The functions, the threshold an the timing of the two interrupt pins (INT 1 and INT 2) can be

completely programmed by the user though the I2C/SPI interface.

4.1

Soldering information

The LGA package is compliant with the ECOPACK, RoHS and “green” standard. It is

qualified for soldering heat resistance according to JEDEC J-STD-020C. Pin #1 indicator is

electrically connected to pin 1. Leave pin 1 indicator unconnected during soldering. Land

pattern and soldering recommendation are available at www.st.com/mems.

Top VIEW

10uF

Vdd

100nF

GND

Vdd_IO

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

TOP VIEW

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

LIS202DL Datasheet(PDF) 11 Page - STMicroelectronics