STA5620

Registers

17/29

7

Registers

7.1

Register map

7.2

PLL N Divider

7.3

PLL R Divider

Note that registers 40, 41 and 42 are delivered on a single 24 bit bus. New register values

are delivered synchronously to the bus only after register 42 is written.

Table 6.

Register map

Address

R/W

Bit

7

6

5

4

321

0

0xC0/40

-

-

-

-

----------------- NDIV[11:8] -----------------

0xC1/41

--------------------------------------------------- NDIV[7:0] ----------------------------------------------------

0xC2/42

-

-

----------------------------------- RDIV[5:0] ----------------------------------

0xC3/43

Reserved

GCE

XCE

LSR

MST

0xD0/50

-

Reserved

IFB

0xD1/51

ENM

Reserved

AGC

IF

MIX

RFA

PLL

VCO

0xD2/52

-

-

-

-------------- LFC[2:0] ---------------

----- CPI[1,0] -----

0xE0/60

RFE

-

Reserved

Table 7.

PLL N divider

Register

address

Name

Bit

Default value

MODE = 0

(decimal)

Default value

MODE = 1

(decimal)

Description

0x40

NDIV

XXXX nnnn [0:3]

96

1555

PLL Feedback Divider Division

Ratio

0x41

nnnn nnnn [0:7]

Table 8.

PLL R divider

Register

address

Name

Bit

Default value

MODE = 0

(decimal)

Default value

MODE = 1

(decimal)

Description

0x42

RDIV

XXrr rrrr [0:5]

1

19

Reference Divider Division

Ratio