MSC8122 datasheet(39/88 Pages) FREESCALE

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AC Timings

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-5

2.5.1

Output Buffer Impedances

2.5.2

Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power.

Section 2.5.3 describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics.

You must use the following guidelines when starting up an MSC8122 device:

•

PORESET

and TRST must be asserted externally for the duration of the power-up sequence. See Table 2-10

for timing.

•

If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up

the VDD levels and then the VDDH levels (see Figure 2-3).

•

CLKIN

should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before

PORESET

deassertion to guarantee correct device operation (see Figure 2-2 and Figure 2-3).

•

CLKIN

must not be pulled high during VDDH power-up. CLKIN can toggle during this period.

The following figures show acceptable start-up sequence examples. Figure 2-2 shows a sequence in which VDD and

VDDH are raised together. Figure 2-3 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle

as VDDH rises.

Table 2-5.

Output Buffer Impedances

Output Buffers

Typical Impedance (

Ω)

System bus

Memory controller

Parallel I/O

Note:

These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.

Figure 2-2.

Start-Up Sequence with VDD and VDDH Raised Together

Time

o.5 V

3.3 V

1.2 V

VDDH Nominal Level

PORESET/TRST Asserted

VDD Nominal Level

CLKIN Starts Toggling

VDD/VDDH Applied

PORESET/TRST Deasserted

2.2 V

VDDH = Nominal Value

VDD = Nominal Value

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