STE2004S datasheet(67/79 Pages) STMICROELECTRONICS

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STE2004S

Electrical characteristics

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7.3

AC operation

VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =25°C;

unless otherwise specified.

Table 28. AC operation

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

Internal oscillator (

Figure 71)

FOSC

Internal oscillator

frequency

VDD = 2.8V

kHz

FEXT

External oscillator

frequency

100

kHz

FFRAME

Frame frequency

fosc or fext = 72 kHz(1)

Tw(RES)

RES LOW pulse width

µs

Reset pulse rejection

µs

TLOGIC

(RES)

Internal logic reset time

µs

TVDD

VDD1 vs. VDD2 Delay

µs

I2C bus interface (

Figure 72)(2) (3)

FSCL

SCL clock frequency

Fast mode

400

kHz

High speed mode;

Cb=100pF (max);(4)

VDD1=2

3.4

MHz

High speed mode;

Cb=400pF (max)(4);

VDD1=2

1.7

MHz

Fast Mode (4);VDD1=1.7V

400

KHz

TSU;STA

Set-up time (repeated)

START condition

Cb = 100pF(5) (6)

160

THD;STA

Hold time (repeated)

START condition

Cb = 100pF(5) (6)

160

TLOW

Low period of SCLH

clock

Cb = 100pF(5) (6)

160

THIGH

High period of SCLH

clock

Cb = 100pF(5) (6)

160

TSU;DAT

Data set-up time

Cb = 100pF(5) (6)

THD;DAT

Data hold time

Cb = 100pF(5) (6)

Tr;CL

Rise time of SCLH signal Cb = 100pF(5) (6)

Tr;CL1

Rise time of SCLH signal

after a repeated START

condition and aftyer an

acknowledge bit

Cb = 100pF(5) (6)

Tf;CL

Fall time of SCLH signal

Cb = 100pF(5) (6)

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