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TMPR3916 Datasheet(PDF) 67 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 67 Page - Toshiba Semiconductor |
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67 / 225 page ![]() Chapter 2 Memory Controller (MC) Preliminary 2-18 Bank Interleaved Read Timing: CLK CS* A BA / A[16:15] CKE RAS* CAS* WE* DQ / D DQM / BE CMD ROW BANK A DataA0 ACT A READ A COLUMN BANK A DataA1 PCHG A ACT B RASL setting CASL setting DataA2 DataA3 DataB0 DataB1 DataB2 DataB3 READ B RASL setting CASL setting ROW BANK B COLUMN BANK B BANK A BANK B PCHG B APL setting APL setting BANK A BANK B PAL seeting ignored due to bank interleaving cycle Figure 2.5.5 Read Access Using Bank Interleaving Auto-Refresh Timing: CLK CS* A BA / A[16:15] CKE RAS* CAS* WE* DQ / D DQM / BE CMD PCHG ROW BANK A Register settings for this example: PAL = 011 bin, ARL = 0010 bin AREF ACT BANK A PAL setting ARL setting Figure 2.5.6 Waveform for Auto-Refresh Timing |
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