TMPR4937 datasheet(161/552 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-5

8.3.2

On-chip Registers

The DMA Controller has two shared registers that are shared by four channels. Section 8.4 explains

each register in detail.

•

Shared Registers

DMMCR:

DMA Master Control Register

DMMFDR:

DMA Memory Fill Data Register

•

DMA Channel Register

DMCHARn:

DMA Chained Address Register

DMSARn:

DMA Source Address Register

DMDARn:

DMA Destination Address Register

DMCNTRn:

DMA Count Register

DMSAIRn:

DMA Source Address Increment Register

DMDAIRn:

DMA Destination Address Increment Register

DMCCRn:

DMA Channel Control Register

DMCSRn:

DMA Channel Status Register

8.3.3

External I/O DMA Transfer Mode

The External I/O DMA Transfer Mode performs DMA transfer with external I/O devices that are

connected to the External Bus Controller.

8.3.3.1

External Interface

External I/O devices signal DMA requests to the DMA Controller by asserting the DMA

Transfer Request Signal (DMAREQ[n]). On the other hand, the DMA Controller accesses external

I/O devices by asserting the DMA Transfer Acknowledge Signal (DMAACK[n]).

The DMA Transfer Request signal (DMAREQ[n]) can use the Request Polarity bit (REQPOL)

of the DMA Channel Control Register (DMCCRn) to select the signal polarity for each channel,

and can use the Edge Request bit (EGREQ) to select either edge detection or level detection for

each channel. The DMA Transfer Acknowledge signal (DMAACK[n]) can also use the

Acknowledge Polarity bit (ACKPOL) to select the polarity.

Please assert/deassert the DMAREQ[n] signal as follows below.

•

When level detection is set (DMCCRn.EGREQ = 0)

The DMAREQ[n] signal must be continuously asserted until one SYSCLK cycle after the

DMAACK[n] signal is asserted. Also, the DMAREQ[n] signal must be deasserted before the

CE*/CS* signal is deasserted. If this signal is asserted too soon, DMA transfer will not be

performed. If this signal is asserted or deasserted too late, unexpected DMA transfer may

result.

During Dual Address transfer, we recommend detecting assertion of the CE* signal for the

external I/O device that is currently asserting DMAACK[n], then deasserting DMAREQ[n].

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