TMPR4937 datasheet(157/552 Pages) TOSHIBA

157 / 552 page

Chapter 8 DMA Controller

8-1

DMA Controller

8.1

Features

The TX4937 contains two four-channel DMA Controller (DMAC0, DMAC1) that executes DMA (Direct

Memory Access) with memory and I/O devices.

The DMA Controller has the following characteristics.

<DMAC0, DMAC1>

•

Has four on-chip DMA channels

•

Supports Memory-Memory Copy modes that do not have address boundary limitations. Burst transfer of

up to eight double words is possible for each Read or Write operation.

•

Supports Memory Fill mode that writes double-word data to the specified memory region

•

Supports Chained DMA Transfer

•

On-chip signed 24-bit address count up registers for both the source address and destination address

•

On-chip 26-bit Byte Count Register for each channel

•

One of two methods can be selected for determining access priority among multiple channels: Round

Robin or Fixed Priority

•

Big Endian or Little Endian mode can be set separately for each channel

<DMAC0>

•

Supports external I/O devices with 8-, 16-, and 32-bit Data Bus widths and transfer between memory

devices.

•

Supports single address transfer (Fly-by DMA) and dual address transfer when in the external I/O DMA

Transfer Mode that is operated by external request signals

•

Supports DMA on-chip Serial I/O Controllers

<DMAC1>

•

Supports DMA on-chip AC-Link Controllers

TMPR4937 Datasheet(PDF) 157 Page - Toshiba Semiconductor