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TMPR4937 Datasheet(PDF) 158 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 158 Page - Toshiba Semiconductor |
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158 / 552 page  Chapter 8 DMA Controller 8-2 8.2 Block Diagram Figure 8.2.1 DMA0 Controller Block Diagram DMA0 Channel 3 DMA0 Channel 2 DM0DAR3 DM0CHAR2 DM0SAR2 DM0DAR2 DM0CNTR2 DM0SAIR2 DM0DAIR2 DM0CCR2 DM0CSR2 DM0CHAR3 DM0SAR3 DM0CNTR3 DM0SAIR3 DM0DAIR3 DM0CCR3 DM0CSR3 DMA Control 0 Block DM0MCR DM0MFDR DMAC0 G-Bus I/F FIFO (8 Double Words) DMA0 Channel 0 DM0CHAR0 DM0SAR0 DM0DAR0 DM0CNTR0 DM0SAIR0 DM0DAIR0 DM0CCR0 DM0CSR0 DREQ0 DACK0 DMAREQ[0] DMAACK[0] PCFG.DMASEL0 External Pins Internal I/O (Receive SIO ch1) DMA0 Channel 1 DM0CHAR1 DM0SAR1 DM0DAR1 DM0CNTR1 DM0SAIR1 DM0DAIR1 DM0CCR1 DM0CSR1 DREQ1 DMCK1 DMAREQ[1] DMAACK[1] PCFG.DMASEL1 DREQ2 DACK2 DMAREQ[2] DMAACK[2] PCFG.DMASEL2 DREQ3 DMCK3 DMAREQ[3] DMAACK[3] PCFG.DMASEL3 DMA Channel Arbiter DMADONE* External Pins External Pins External Pins External Pins Internal I/O (Transfer SIO ch1) Internal I/O (Receiver SIO ch0) Internal I/O (Transfer SIO ch0) |
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