TMPR4937 datasheet(268/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-10

Table 10.3.3 Initiator Access Space Properties Register

Enable

Word Swap

Memory Space 0

BusMasterEnable

& PCICCFG.G2PM0EN

G2PM0GBASE.BSWAP

Memory Space 1

BusMasterEnable

& PCICCFG.G2PM1EN

G2PM1GBASE.BSWAP

Memory Space 2

BusMasterEnable

& PCICCFG.G2PM2EN

G2PM2GBASE.BSWAP

I/O Space

BusMasterEnable

& PCICCFG.G2PIOEN

G2PIOGBASE.BSWAP

BusMasterEnable

Host mode:

PCI State Command Register Bus Master Bit (PCISTATUS.BM)

Satellite mode: Command Register Bus Master bit

10.3.5 Target Access (PCI Bus → G-Bus Address Conversion)

During PCI target access, the PCI Bus address of the Bus transaction issued by the PCI Bus is

converted into a G-Bus address and is used to issue a Bus transaction on the G-Bus. 40-bit PCI Bus

addresses are used on the PCI Bus. Also, 36-bit physical addresses are used on the G-Bus.

Three memory access windows and one I/O access window can be set in the PCI bus space (Figure

10.3.5). The size of each window is fixed. When Bus transactions to these access windows is issued on

the PCI Bus, these Bus transactions are accepted as PCI target devices. The PCI Bus Address is

converted into G-Bus addresses, then Bus transactions are issued to the G-Bus.

The memory space window responds to the PCI memory space access command. The I/O space

window responds to the PCI I/O space access command.

Note: Byte swapping is always disabled when prefetch mode is disabled. When the G-Bus is

configured for big-endian mode, the order of bits in a 32-bit word does not change

during a PCI transfer. (The byte ordering changes.)

Figure 10.3.5 Target Access Memory Window

0x00_0000_0000

0xFF_FFFF_FFFF

0x0_0000_0000

0x00_0000_0000

0xFF_FFFF_FFFF

0xF_FFFF_FFFF

PCI I/O Space

G-Bus Space

PCI Memory Space

Memory Access Window

I/O Access Window

0x00_FFFF_FFFF

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