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UPSD3422 Datasheet(PDF) 156 Page - STMicroelectronics

Part # UPSD3422
Description  Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic
PDF  293 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3422 Datasheet(HTML) 156 Page - STMicroelectronics

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USB interface
uPSD34xx
156/293
The USB interrupt priority can be set to low or high. For the best USB response time and to
maximize data transfer times, the USB interrupt should be set to the highest priority (see the
Section 13: Interrupt system for the details on setting the interrupt priority).
●
USB Reset Interrupt
The host signals a bus reset by driving both D+ and D– low for at least 10ms. When
the uPSD34xx’s SIE detects a reset on the USB, it generates the RST interrupt
request. A USB reset does not reset the CPU nor the USB SIE, nor does it disable the
USB SIE. The interrupt service routine should disable/enable the USB SIE to reset a
portion of the state machine and initialize the USB SIE registers per the application
requirements.
●
USB Suspend Interrupt
If the uPSD34xx’s SIE detects 3ms of no activity on the bus, it generates the
SUSPEND interrupt request. It also causes the clock to the SIE to shut down to
conserve power.
●
USB EOP (End of Packet) Interrupt
Every packet sent on the USB includes a signal, called EOP, to indicate the end of the
packet. When an EOP is detected, the SIE generates an EOP interrupt.
●
USB Resume Interrupt
When USB activity is detected and the SIE is in the suspend state, a RESUME
interrupt is generated. The USB Resume interrupt service routine should clear the
SUSPENDF bit in the UIF0 register if it is set in order to turn the USB SIE clock on.
●
USB Global Interrupt Enable Register (UIE0)
There are four USB events that are considered to be global in nature, meaning they are
not specific to an endpoint, but apply to the USB bus in general. The four global USB
events include Reset, Suspend, EOP, and Resume.
Each event can be enabled to generate an interrupt using the UIE0 register shown in
Table 72
Table 72.
USB global interrupt enable register (UIE0 0E4h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
––
–
–
RSTIE
SUSPEND
IE
EOPIE
RESUMIE
Bit
Symbol
R/W
Definition
7
–
–
Reserved
6
–
–
Reserved
5
–
–
Reserved
4
–
–
Reserved
3
RSTIE
R/W
Enable the USB Reset interrupt
2
SUSPEND
IE
R/W
Enable the USB Suspend interrupt
1
EOPIE
R/W
Enable the USB EOP interrupt
0
RESUMIE
R/W
Enable the USB Resume interrupt



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