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TMP93CS44 Datasheet(PDF) 214 Page - Toshiba Semiconductor |
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TMP93CS44 Datasheet(HTML) 214 Page - Toshiba Semiconductor |
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214 / 224 page  TMP93CS44/S45 2004-02-10 93CS44-212 (10) AD converter control Symbol Name Address 7 6 5 4 3 2 1 0 EOCF AD8F − − ITM0 REPET SCAN ADS R R/W 0 0 0 0 0 0 0 0 ADMOD 0 AD mode control register 0 5EH 1: End 1: Busy Always write “0”. Always write “0”. 0: Every conversion 1: Every four conversion 0: Single 1: Repeat 0: fixed- channel 1: Scan 1: START VREFON ADTRGE ADCH2 ADCH1 ADCH0 R/W R/W 1 0 0 0 0 ADMOD 1 AD mode control register 1 5FH 0: OFF 1: ON External trigger start control 0: Disable 1: Enable Analog input channel selection ADR01 ADR00 ADR0RF R R Undefined 0 *1) AD REG04L AD conversion result register 0/4 low 60H Stores lower two bits of AD conversion result Conversion result stored flag ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 R Undefined AD REG04H AD conversion result register 0/4 high 61H Stores upper eight bits of AD conversion result ADR11 ADR10 ADR1RF R R Undefined 0 *1) AD REG15L AD conversion result register 1/5 low 62H Stores lower two bits of AD conversion result Conversion result stored flag ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 R Undefined AD REG15H AD conversion result register 1/5 high 63H Stores upper eight bits of AD conversion result ADR21 ADR20 ADR2RF R R Undefined 0 *1) AD REG26L AD conversion result register 2/6 low 64H Stores lower two bits of AD conversion result Conversion result stored flag ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 R Undefined AD REG26H AD conversion result register 2/6 high 65H Stores upper eight bits of AD conversion result ADR31 ADR30 ADR3RF R R Undefined 0 *1) AD REG37L AD conversion result register 3/7 low 66H Stores lower two bits of AD conversion result Conversion result stored flag ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 R Undefined AD REG37H AD conversion result register 3/7 high 67H Stores upper eight bits of AD conversion result ADREGxH 765 432 10 7 6 5 4 3 2 1 0 ADREGxL Converted data of channel x 7 654 321 0 98 *1: Data to be stored in AD conversion result register low are the lower 2 bits of the conversion result. The contents of the 5 to 1 bits of this register are always read as 1. Bit0 conversion result stored flag bit <ADRxRF>, <ADRxRF> is set to 1 when the AD conversion result is stored. Reading either the ADREGxH or the ADREGxL registers clears <ADRxRF> to 0. This is “1” when this is read. |
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