MCP3460R datasheet(72/103 Pages) MICROCHIP

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MCP3460R

DS20006975A page 72

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IRQ pin state. The interrupt generates an IRQ

pin falling edge (transition to logic low) as soon

as it happens.

The data ready interrupt is cleared by the first of the

following two events:

• First falling edge of SCK during an ADC Output

Data register read

• 16 DMCLK clock periods before current

conversion ends

If the user does not read the ADCDATA register in time

in Continuous Conversion mode or in Scan mode, the

IRQ pin will automatically reset to its Inactive state

16 DMCLKs, prior to the new data ready interrupt. This

feature is designed in order to avoid the case where the

IRQ pin is logic low if the reading of ADC data is not

performed. The user can then determine exactly when

to expect the new data and can respect the tDODR

timing in all cases to ensure a proper reading of the

ADC data. See Figure 6-13 for more details.

FIGURE 6-13:

Data Ready Interrupt IRQ Pin Timing Diagram.

6.8.2

CONVERSION CYCLE START

INTERRUPT

This interrupt is the only selectable one and the only

one not present in the STATUS byte on the SDO and

IRQ registers. It is only available on the IRQ pin. The

user can enable or disable this output by using:

•[EN_STP] = 1: The conversion start interrupt

output is enabled (default).

•[EN_STP] = 0: The conversion start interrupt

output is disabled.

This interrupt marks the beginning of a conversion

cycle. In case of a One-Shot mode or Continuous mode

conversion in MUX mode, it marks the start of the

sampling in the first conversion (after the ADC start-up

delay of 256 DMCLK periods). In case of a Scan mode,

it marks the start of the sampling in the first conversion

of the first Scan mode cycle. The host MCU can utilize

this interrupt to synchronize the start of the ADC con-

version and manage synchronous events together with

the conversion process (see Figure 6-15 for more

details).

FIGURE 6-14:

Conversion Start IRQ Timing Diagram.

This interrupt marks the beginning of a conversion

cycle. In case of a One-Shot mode or Continuous mode

conversion in MUX mode, it marks the start of the

sampling in the first conversion (after the ADC start-up

delay of 256 DMCLK periods). In case of a Scan mode,

it marks the start of the sampling in the first conversion

of the first Scan mode cycle. The host MCU can utilize

this interrupt to synchronize the start of the ADC con-

version and manage synchronous events together with

the conversion process (see Figure 6-15 for more

details).

SPI

IRQ

TCON V

Transition time

tDOD R

Read A DC DATA1

1/DRCLK

TDRH

DATA1 can be read dur ing this time

Interrupt is cleared

at first SCK falling edge

after ADCDATA read start

ADCDATA

DATA1

DATA0

Interrupt is cleared

automatically if ADCDATA

has not been read in time

Read A DC DATA2

1/DRCLK

TDRH

DATA2 can be read dur ing this time

DATA2

Data Ready Interrupt

C OMM AN D By te

Read A DCDATA

C OMM AN D By te

Read A DCDATA

Transition time

tDOD R

ADC_MODE

IRQ

TADC_SETUP

TCON V

TSTP

Conversion

Start IRQ

(EN_STP = 1)

Data Ready

IRQ

Shu tdo wn

ADC STATUS

1st Co nv ers ion in

either MU X or SCAN mode

Start-u p

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