MCP3460R datasheet(80/103 Pages) MICROCHIP

80 / 103 page

MCP3460R

DS20006975A page 80

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8.1

ADCDATA REGISTER

Name

Bits

Address

Cof

ADCDATA

4/16/32

0x0

ADCDATA: ADC CHANNEL DATA OUTPUT REGISTER

R-0

ADCDATA[15:8]

bit 15

bit 8

R-0

ADCDATA[7:0]

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-0

ADCDATA[15:0]: ADC Output Code

The data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. The data can be

formatted in 16-bit or 32-bit modes depending on the setting of the DATA_FORMAT[1:0] bits in the

CONFIG3 register (see Section 5.6 “ADC Output Data Format”).

The ADC Channel Data Output register always contains the most recent Analog-to-Digital (A/D)

conversion data. The register is updated at each data ready internal signal and depends on the values

of the OSR bit in the CONFIG1 register and the CONV_MODE bit in the CONFIG3 register. The ADC

Channel Data Output register is latched at the start of each SPI Read command. The register is double

buffered to avoid data loss. There is a small time delay, tDODR, after each data ready, when to wait for

the data to be available. Otherwise, data corruption can occur when the internal data are refreshed.

When IRQ_MODE[1:0] = 1x in the IRQ register, the ADC Channel Data Output register becomes a

4-bit wide register containing the MDAT output codes. These codes are the outputs of the modulator,

represented by four comparator outputs (COMP[3:0], see Section 5.4.2 “Modulator Output Block”).

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