ADG901/ADG902

Data Sheet

Rev. D | Page 6 of 13

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NOTES

1. THE LFCSP PACKAGE HAS AN EXPOSED

PAD. THE EXPOSED PAD MUST BE TIED

TO THE SUBSTRATE, GND.

3

4

1

2

6

5

8

7

VDD

CTRL

GND

RF1

RF2

GND

GND

GND

TOP VIEW

(Not to Scale)

ADG901

Figure 4. 8-Lead LFCSP Pin Configuration

ADG901/

ADG902

TOP VIEW

(Not to Scale)

VDD

CTRL

GND

RF1

RF2

GND

GND

GND

1

2

3

4

8

7

6

5

Figure 5. 8-Lead MSOP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VDD

Power Supply Input. These devices can be operated from 1.65 V to 2.75 V; decouple VDD to GND.

2

CTRL

CMOS or LVTTL Logic Level. CTRL input must not exceed VDD.

Logic 0: RF1 isolated from RF2.

Logic 1: RF1 to RF2.

3, 5, 6, 7

GND

Ground Reference Point for All Circuitry on the Device.

4

RF1

RF1 Port.

8

RF2

RF2 Port.

EPAD

Exposed Pad. The LFCSP package has an exposed pad. The exposed pad must be tied to the substrate, GND.

Table 5. Truth Table

CTRL

Signal Path

0

RF1 isolated from RF2

1

RF1 to RF2